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| Datasheet File OCR Text: |
| july 2001 1/103 this is preliminary information on a new product now in development. details are subject to change without notice. L9805 super smart power motor driver with 8-bit mcu, can interface, 16k eprom, 256bytes ram, 128 bytes eeprom, 10 bit adc, wdg, 2 timers, 2 pwm modules, full h-bridge driver prouct preview n 6.4-18v supply operating range n 16 mhz maximum oscillator frequency n 8 mhz maximum internal clock frequency n oscillator supervisor n fully static operation n -40c to + 150c temperature range n user eprom/otp: 16 kbytes n data ram: 256 bytes n data eeprom: 128 bytes n 64 pin hiquad64 package n 10 multifunctional bidirectional i/o lines n two 16-bit timers, each featuring: C 2 input captures C 2 output compares C external clock input (on timer 1) C pwm and pulse generator modes n two programmable 16-bit pwm generator modules. n can peripheral including bus line interface according 2a/b passive specifications n 10-bit analog-to-digital converter n software watchdog for system integrity n master reset, power-on reset, low voltage reset n 70m w dmos h-bridge. n 8-bit data manipulation n 63 basic instructions and 17 main addressing modes n 8 x 8 unsigned multiply instruction n true bit manipulation n complete development support on dos/ windows tm real-time emulator n full software package on dos/windows tm (c-compiler, cross-assembler, debugger) hiquad-64 ordering number: L9805 1
2/103 table of contents 103 L9805 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 otp, rom and eprom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 pin out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 clocks, reset, interrupts & power saving modes . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 oscillator safeguard (dcsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 dedicated control status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 watchdog system (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 3.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 miscellaneous register (miscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 3.5.3 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.4 power-on reset - low voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 digital section power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.1 vdd short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 analog section power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 vcc short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/103 table of contents L9805 5.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 5.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.4 pwm i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4.2 pwmo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4.3 pwmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5 10-bit a/d converter (ad10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5.3 input selections and sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.5.4 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.5.5 temperature sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.5.6 precise temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.6 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 5.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.7 can bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 5.7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7.4 can transceiver disabling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.8 power bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 5.8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8.4 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.8.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.8.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.9 eeprom (eep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.9.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4/103 L9805 7.3 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4 application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7 operating block electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 100 5/103 L9805 1 general description 1.1 introduction the L9805 is a super smart power device suited to drive resistive and inductive loads under soft- ware control. it includes a st7 microcontroller and some pheripherals. the microcontroller can exe- cute the software contained in the program eprom/rom and drive, through dedicated regis- ters, the power bridge. the internal voltage regulators rated to the auto- motive environment, pwm modules, can trans- ceiver and controller, iso 9141 transceiver, tim- ers, temperature sensor and the atod converter allow the device to realize by itself a complete ap- plication, in line with the most common mechatron- ic requirements. 1.2 otp, rom and eprom devices for development purposes the device is available in plastic hiquad package without window rating in the otp class. mass production is supported by means of rom devices. engineering samples could be assembled using window packages. these are generally referenced as eprom devices. eprom devices are erased by exposure to high intensity uv light admitted through the transparent window. this exposure discharges the floating gate to its initial state through induced photo cur- rent. it is recommended to keep the L9805 device out of direct sunlight, since the uv content of sunlight can be sufficient to cause functional failure. ex- tended exposure to room level fluorescent lighting may also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. covering the window also reduces i dd in power-saving modes due to photo-diode leakage currents. an ultraviolet source of wave length 2537 ? yield- ing a total integrated dosage of 15 watt-sec/cm 2 is required to erase the eprom. the device will be erased in 40 to 45minutes if such a uv lamp with a 12mw/cm 2 power rating is placed 1 inch from the device window without any interposed filters. otp and eprom devices can be programmed by a dedicated eprom programming board and soft- ware that are part of the development tool-set. 6/103 L9805 figure 1. L9805 block diagram 8-bit core alu address and data bus oscin oscout 10-bit adc watchdog osc internal clock control rom/otp/eprom 16k port a pa0 -> pa7 osc safeguard port b pb0 -> pb1 timer 1 timer 2 pwm 2 pwm 1 pwmi pwmo pwmo ad2 ad3 ad4 ram 256b eeprom 128b v cc v dd power supply vb2 preregulator agnd gnd nreset power bridge vbr vbl pgnd outr outl can controller can transceiver can_h can_l rx tx temp sensor pwmi vpp/tm vb1 7/103 L9805 1.3 pin out. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 nu nu nu ad3 ad2 pa1/ocmp1_1 pa0/ocmp2_1 vpp/tm vdd oscin oscout gnd nu vbl vbl vbl nu nu nu nu nu pb1/extclk_2 nu nu pwmo pwmi nreset can_h can_l gnd vdd vb2 vb1 vbr vbr vbr nu nu nu nu nu nu outl outl outl pgnd pgnd outr outr outr nu nu vcc agnd ad4 pa2/icap2_1 pa3/icap1_1 pgnd pgnd pa4/extclk_1 pa5/ocmp2_2 pa6/ocmp1_2 pa7/icap2_2 pb0/icap1_2 8/103 L9805 1.4 pin description ad2-ad4: analog input to adc. pa0/ocmp2_1-pa1/ocmp1_1: i/os or output compares on timer 1. alternate function software selectable (by setting oc2e or oc1e in cr2 reg- ister: bit 6 or 7 at 0031h). when used as an alter- nate function, this pin is a push-pull output as re- quested by timer 1. otherwise, this pin is a trig- gered floating input or a push-pull output. pa2/icap2_1-pa3/icap1_1: i/ os or input cap- tures on timer 1. before using this i/o as alternate inputs, they must be configured by software in in- put mode (ddr=0). in this case, these pins are a triggered floating input. otherwise (i/o function), these pin are triggered floating inputs or push-pull outputs. pa4/extclk_1: pa4 i/o or external clock on timer 1 . before using this i/o as alternate input, it must be configured by software in input mode (ddr=0). in this case, this pin is a triggered float- ing input. otherwise (i/o function), this pin is a trig- gered floating input or a push-pull output. pa5/ocmp2_2-pa6/ocmp1_2: i/os or output compares on timer 2 . alternate function software selectable (by setting oc2e or oc1e in cr2 reg- ister: bit 6 or 7 at 0041h). when used as alternate functions, these pins are push-pull outputs as re- quested by timer 2. otherwise, these pins are trig- gered floating inputs or push-pull outputs. pa7/icap2_2-pb0/icap1_2: i/os or input cap- tures on timer 2 . before using these i/os as alter- nate inputs, they must be configured by software in input mode (ddr=0). in this case, these pins are triggered floating inputs. otherwise (i/o func- tion), these pins are triggered floating inputs or push-pull outputs. pb1/extclk_2: pb1 i/o or external clock on timer 2 . before using this i/o as alternate input, it must be configured by software in input mode (ddr=0). in this case, this pin is a triggered float- ing input. otherwise (i/o function), this pin is a trig- gered floating input or a push-pull output. vpp/tm : input. this pin must be held low during normal operating modes. vdd : output. 5v power supply for digital circuits, from internal voltage regulator. oscin: input oscillator pin. oscout : output oscillator pin. gnd: ground for digital circuits. vbr: power supply for right half-bridge. outr: output of left half-bridge. pgnd: ground for power transistor. outl: output of right half-bridge. vbl: power supply for left half-bridge. vb1 : power supply for voltage regulators. vb2 : pre-regulated voltage for analog circuits. can_l: low side can bus output. can_h: high side can bus input. nreset: bidirectional. this active low signal forc- es the initialization of the mcu. this event is the top priority non maskable interrupt. it can be used to reset external peripherals. pwmi: pwm input. directly connected to input capture 2 on timer 2. pwmo: pwm output. connected to the output of pwm2 module. agnd: ground for all analog circuitry (except power bridge) . vcc: output. 5v power supply for analog circuits, from internal voltage regulator. 9/103 L9805 1.5 register & memory map as shown in the table 1 , the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. in this mcu, 63742 of these bytes are user accessible. the available memory locations consist of 128 bytes of i/o registers, 256 bytes of ram, 128 bytes of eeprom and 16kbytes of user eprom/ rom. the ram space includes 64bytes for the stack from 0140h to 017fh. the highest address bytes contain the user reset and interrupt vectors. table 1. memory map address block register la- bel register name reset status remarks 0000h 0001h 0002h 0003h port a padr .. paddr .. paor .. data register data direction register option register not used 00h 00h 00h r/w r/w r/w absent 0004h 0005h 0006h 0007h port b pbdr .. pbddr .. pbor .. data register data direction register option register not used 00h 00h 00h r/w r/w r/w absent 0008h to 000fh reserved 0010h 0011h 0012h 0013h 0014h 0015h 0016h pwm1 p1cyrh .. p1cyrl .. p1drh .. p1drl .. p1cr .. p1cth .. p1ctl .. pwm1 cycle register high pwm1 cycle register low pwm1 duty register high pwm1 duty register low pwm1 control register pwm1 counter register high pwm1 counter register low 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w read only read only 0017h reserved 0018h 0019h 001ah 001bh 001ch 001dh 001eh pwm2 p2cyrh .. p2cyrl .. p2drh .. p2drl .. p2cr .. p2cth .. p2ctl .. pwm2 cycle register high pwm2 cycle register low pwm2 duty register high pwm2 duty register low pwm2 control register pwm2 counter register high pwm2 counter register low 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w read only read only 001fh reserved 0020h miscr .. miscellaneous register 00h see section 3.4 0021h power bridge pbcsr .. bridge control status register 00h r/w 0022h dcsr .. dedicated control status register 00h r/w 0023h to 0029h reserved 002ah 002bh wdg wdgcr .. wdgsr .. watchdog control register watchdog status register 7fh 00h r/w r/w 002ch eeprom eecr .. eeprom control register 00h r/w 002dh 002eh eprom ecr1 ecr2 eprom control register 1 eprom control register 2 st internal use only 002fh 0030h crc crcl crch crcl test register crch test register st internal use only 10/103 L9805 0031h 0032h 0033h 0034h-0035h 0036h-0037h 0038h-0039h 003ah-003bh 003ch-003dh 003eh-003fh tim1 t1cr2 .. t1cr1 .. t1sr .. t1ic1hr .. t1ic1lr .. t1oc1hr .. t1oc1lr .. t1chr .. t1clr .. t1achr .. t1aclr .. t1ic2hr .. t1ic2lr .. t1oc2hr .. t1oc2lr .. timer 1 control register2 timer 1 control register1 timer 1 status register timer 1 input capture1 high register timer 1 input capture1 low register timer 1 output compare1 high register timer 1 output compare1 low register timer 1 counter high register timer 1 counter low register timer 1 alternate counter high register timer 1 alternate counter low register timer 1 input capture2 high register timer 1 input capture2 low register timer 1 output compare2 high register timer 1 output compare2 low register 00h 00h xxh xxh xxh xxh xxh ffh fch ffh fch xxh xxh xxh xxh r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved: write forbidden 0041h 0042h 0043h 0044h-0045h 0046h-0047h 0048h-0049h 004ah-004bh 004ch-004dh 004eh-004fh tim2 t2cr2 .. t2cr1 .. t2sr .. t2ic1hr .. t2ic1lr .. t2oc1hr .. t2oc1lr .. t2chr .. t2clr .. t2achr .. t2aclr .. t2ic2hr .. t2ic2lr .. t2oc2hr .. t2oc2lr .. timer 2 control register2 timer 2 control register1 timer 2 status register timer 2 input capture1 high register timer 2 input capture1 low register timer 2 output compare1 high register timer 2 output compare1 low register timer 2 counter high register timer 2 counter low register timer 2 alternate counter high register timer 2 alternate counter low register timer 2 input capture2 high register timer 2 input capture2 low register timer 2 output compare2 high register timer 2 output compare2 low register 00h 00h xxh xxh xxh xxh xxh ffh fch 00h 00h xxh xxh xxh xxh r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h to 0059h reserved 005ah 005bh 005ch 005dh 005eh 005fh 0060h to 006fh can canisr .. canicr .. cancsr .. canbrpr .. canbtr .. canpsr .. can interrupt status register can interrupt control register can control/status register can baud rate prescaler can bit timing register can page selection can first address to last address of page x 00h 00h 00h 00h 23h 00h -- r/w r/w r/w r/w r/w r/w see page map- ping and regis- ter description 0070h 0071h 0072h adc adcdrh .. adcdrl .. adccsr .. adc data register high adc data register low adc control/status register 00h 00h 20h read only read only r/w address block register la- bel register name reset status remarks 11/103 L9805 address block description 0080h to 013fh ram 256 bytes including stack 64 bytes (0140h to 017fh) user variables and subroutine nesting 0140h to 017fh 0180h to 0bffh reserved 0c00h to 0c7fh eeprom 128 bytes including 4 bytes reserved for temperature sensor trimming (see section 5.5.6 ) 0c7ch: t0h 0c7dh: t0l 0c7eh: vt0h 0c7fh: vt0l 0c80h to bfffh reserved c000 to ffdfh eprom 16k bytes (16384 bytes) user application code and data ffe0h to ffffh interrupt and reset vectors 12/103 L9805 2 central processing unit 2.1 introduction the cpu has a full 8-bit architecture. six internal registers allow efficient 8-bit data manipulation. the cpu is capable of executing 63 basic instruc- tions and features 17 main addressing modes. 2.2 cpu registers the 6 cpu registers are shown in the program- ming model in figure 2, on page 12. following an interrupt, all registers except y are pushed onto the stack in the order shown in figure 3, on page 13. they are popped from stack in the re- verse order. the y register is not affected by these automatic procedures. the interrupt routine must therefore handle y, if needed, through the push and pop instructions. accumulator (a). the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calcula- tions as well as data manipulations. index registers (x and y). these 8-bit registers are used to create effective addresses or as tem- porary storage areas for data manipulation. the cross-assembler generates a precede instruc- tion (pre) to indicate that the following instruction refers to the y register. program counter (pc). the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. figure 2. organization of internal cpu registers accumulator: x index register: y index register: stack pointer: condition code register: program counter: x = undefined 15 reset value: 70 xx xxxxxx reset value: 70 1x 11x1xx 1c 1 1 hi nz reset value = reset vector @ fffeh-ffffh reset value: 70 xx xxxxxx reset value: 70 xx xxxxxx 70 15 70 01 000000 reset value =0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 13/103 L9805 cpu registers (contd) stack pointer (sp) the stack pointer is a 16-bit register. since the stack is 64 bytes deep, the most significant bits are forced as indicated in figure 2, on page 12 in order to address the stack as it is mapped in memory. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer is set to point to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the upper and lower limits of the stack area are shown in the memory map. the stack is used to save the cpu context during subroutine calls or interrupts. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an in- terrupt (refer to figure 3 ), the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations. C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. condition code register (cc) the condition code register is a 5-bit register which indicates the result of the instruction just executed as well as the state of the processor. these bits can be individu- ally tested by a program and specified action taken as a result of their state. the following paragraphs describe each bit of the cc register in turn. half carry bit (h) the h bit is set to 1 when a carry occurs between bits 3 and 4 of the alu during an add or adc instruction. the h bit is useful in bcd arithmetic subroutines. interrupt mask (i) when the i bit is set to 1, all in- terrupts except the trap software interrupt are disabled. clearing this bit enables interrupts to be passed to the processor core. interrupts requested while i is set are latched and can be processed when i is cleared (only one interrupt request per in- terrupt enable flag can be latched). negative (n) when set to 1, this bit indicates that the result of the last arithmetic, logical or data ma- nipulation is negative (i.e. the most significant bit is a logic 1). zero (z) when set to 1, this bit indicates that the result of the last arithmetic, logical or data manipu- lation is zero. carry/borrow (c) when set, c indicates that a carry or borrow out of the alu occured during the last arithmetic operation. this bit is also affected during execution of bit test, branch, shift, rotate and store instructions. figure 3. stack manipulation on interrupt condition code accumulator x index register pch pcl 111 0 7 higher address lower address context restored context saved on interrupt on return 14/103 L9805 3 clocks, reset, interrupts & power saving modes 3.1 clock system 3.1.1 general description the mcu accepts either a crystal or ceramic res- onator, or an external clock signal to drive the in- ternal oscillator. the internal clock (f cpu ) is de- rived from the external oscillator frequency (f osc ) . the external oscillator clock is first divided by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in slow mode, to reduce the fre- quency of the f cpu ; this clock signal is also routed to the on-chip peripherals (except the can). the cpu clock signal consists of a square wave with a duty cycle of 50%. the internal oscillator is designed to operate with an at-cut parallel resonant quartz crystal resona- tor in the frequency range specified for f osc . the circuit shown in figure 5 is recommended when using a crystal, and table 2 lists the recommend- ed capacitance and feedback resistance values. the crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. use of an external cmos oscillator is recom- mended when crystals outside the specified fre- quency ranges are to be used. table 2. recommended values for 16 mhz crystal resonator note: r smax is the equivalent serial resistor of the crystal (see crystal specification). c oscin ,c oscout : maximum total capacitances on pins oscin and oscout (the value includes the external capacitance tied to the pin plus the para- sitic capacitance of the board and of the device). rp: external shunt resistance. recommended val- ue for oscillator stability is 1m w . figure 4. external clock source connections figure 5. crystal/ceramic resonator figure 6. clock prescaler block diagram r smax 40 w 60 w 150 w c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf r p 1-10 m w 1-10 m w 1-10 m w osc in osc out external clock nc osc in osc out c oscin c oscout r p osc in osc out c oscin c oscout r p %2 %2,4,8,16 cpuclk to cpu and peripherals to can 15/103 L9805 clock system (contd) 3.1.2 external clock an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 4 . the t oxov specifications does not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov (see ). figure 7. timing diagram for internal cpu clock frequency transitions b1 : b2 miscellaneous register 00 01 b0 1 1 0 osc/2 osc/4 osc/8 cpu clk vr02062b new frequency requested new frequency active when osc/4 & osc/8 = 0 normal mode active (osc/4 - osc/8 stoppe d normal mode requested 16/103 L9805 3.2 oscillator safeguard the L9805 contains an oscillator safe guard func- tion. this function provides a real time check of the crystal oscillator generating a reset condition when the clock frequency has anomalous value. if f osc 17/103 L9805 3.3 watchdog system (wdg) 3.3.1 introduction the watchdog is used to detect the occurrence of a software fault, usually generated by external in- terference or by unforeseen logical conditions, which causes the application program to give up its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time pe- riod, unless the program refreshes the counters contents before it is decremented to zero. 3.3.2 main features C programmable timer (64 increments of 12,288 cpu clock) C programmable reset C reset (if watchdog activated) after an halt in- struction or when bit timer msb reaches zero C watchdog reset indicated by status flag. 3.3.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 1): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t5:t0 bit contain the number of increments which represents the time delay before the watchdog produces a reset. table 3. watchdog timing (f osc = 16 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. figure 8. functional description wdg register initial value wdg timeout period (ms) 7fh 98.3 c0h 1.54 reset wdga 7-bit downcounter f cpu msb lsb clock divider wdgf watchdog status register (wdgsr) watchdog control register (wdgcr) ? 12288 18/103 L9805 watchdog system (contd) the watchdog delay time is defined by bits 5-0 of the watchdog register; bit 6 must always be set in order to avoid generating an immediate reset. conversely, this can be used to generate a soft- ware reset (bit 7 = 1, bit 6 = 0). the watchdog must be reloaded before bit 6 is dec- remented to 0 to avoid a reset. following a re- set, the watchdog register will contain 7fh (bits 0- 7). if the circuit is not used as a watchdog (i.e. bit 7 is never set), bits 6 to 0 may be used as a simple 7- bit timer, for instance as a real time clock. since no reset will be generated under these conditions, the watchdog control register must be monitored by software. a flag in the watchdog status register indicates if the last reset is a watchdog reset or not, before clearing by a write of this register. 3.3.4 register description 3.3.4.1 watchdog control register (wdgcr) register address: 002ah read/write reset value: 0111 1111 (7fh) b7 = wdga: activation bit. this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled. b6-0 = t6-t0 : 7 bit timer (msb to lsb) these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 become cleared). 3.3.4.2 watchdog status register (wdgsr) register address: 002bh read/write reset value (*) : 0000 0000 (00h) b7-1 = not used b0 = wdgf: watchdog flag. set by a watchdog reset, cleared by software (writing zero) or power on / low voltage reset. this flag is useful for dis- tinguishing power on / low voltage reset and watchdog reset. (*): except in the case of watchdog reset. 70 wdgat6t5t4t3t2t1t0 70 -------wdgf 19/103 L9805 3.4 miscellaneous register (miscr) the miscellaneous register allows the user to se- lect the slow operating mode and to set the clock division prescaler factor. bits 3, 4 determine the signal conditions which will trigger an interrupt re- quest on i/o pins having interrupt capability. register address: 0020h read/write reset value:0000 0000 (00h) b0 - slow mode select 0- normal mode - oscillator frequency / 2 (reset state) 1- slow mode (bits b1 and b2 define the prescaler factor) b1, b2 - cpu clock prescaler for slow mode the selection issued from b3/b4 combination is applied to pa[0]..pa[7],pb0,pb1 external inter- rupt. the selection can be made only if i bit in cc register is reset (interrupt enabled). b3, b4 can be written only when the interrupt mask (i) of the cc (condition code) register is set to 1. b5,b6,b7 = not used b7 b6 b5 b4 b3 b2 b1 b0 b2 b1 option 00 oscillator frequency / 4 10 oscillator frequency / 8 01 oscillator frequency / 16 11 oscillator frequency / 32 b4 b3 option 00 falling edge and low level (reset state) 10 falling edge only 01 rising edge only 11 rising and falling edge 20/103 L9805 3.5 reset 3.5.1 introduction there are four sources of reset: C nreset pin (external source) C power-on reset / low voltage detection (inter- nal source) C watchdog (internal source) C safeguard (internal source) the reset service routine vector is located at ad- dress fffeh-ffffh. 3.5.2 external reset the nreset pin is both an input and an open- drain output with integrated pull-up resistor. when one of the internal reset sources is active, the re- set pin is driven low to reset the whole application. 3.5.3 reset operation the duration of the reset condition, which is also reflected on the output pin, is fixed at 4096 internal cpu clock cycles. a reset signal originating from an external source must have a duration of at least 1.5 internal cpu clock cycles in order to be recog- nised. at the end of the power-on reset cycle, the mcu may be held in the reset condition by an ex- ternal reset signal. the nreset pin may thus be used to ensure v dd has risen to a point where the mcu can operate correctly before the user pro- gram is run. following a power-on reset event, or after exiting halt mode, a 4096 cpu clock cycle delay period is initiated in order to allow the oscil- lator to stabilise and to ensure that recovery has taken place from the reset state. during the reset cycle, the device reset pin acts as an output that is pulsed low. in its high state, an internal pull-up resistor of about 300k w is con- nected to the reset pin. this resistor can be pulled low by external circuitry to reset the device. 3.5.4 power-on reset - low voltage detection the por/lvd function generates a static reset when the supply voltage is below a reference val- ue. in this way, the power-on reset and low volt- age reset function are provided, in order to keep the system in safe condition when the voltage is too low. the power-up and power-down thresholds are different, in order to avoid spurious reset when the mcu starts running and sinks current from the supply. the lvd reset circuitry generates a reset when v dd is below: C v reseton when v dd is rising C v resetoff when v dd is falling the por/lvd function is explained in figure 9 . power-on reset activates the reset pull up tran- sistor performing a complete chip reset. in the same way a reset can be triggered by the watch- dog, by the safeguard or by external low level at nreset pin. an external capacitor connected be- tween nr eset and ground can extend the power on reset period if required. 21/103 L9805 figure 9. power up/down behaviour figure 10. reset block diagram = undefined value 5v t v reset ud v reset off v reset on 5v t v dd por/lvd internal reset oscillator signal counter nreset to st7 reset v dd watchdog reset safeguard reset por/lvd reset 300k reset clk 22/103 L9805 3.6 interrupts a list of interrupt sources is given in table 4 below, together with relevant details for each source. in- terrupts are serviced according to their order of pri- ority, starting with i0, which has the highest priori- ty, and so to i12, which has the lowest priority. the following list describes the origins for each in- terrupt level: C i0 connected to ports pa0-pa7, pb0-pb1 C i1 connected to can C i2 connected to power diagnostics C i3 connected to output compare of timer 1 C i4 connected to input capture of timer 1 C i5 connected to timer 1 overflow C i6 connected to output compare of timer 2 C i7 connected to input capture of timer 2 C i8 connected to timer 2 overflow C i9 connected to adc end of conversion C i10 connected to pwm 1 overflow C i11 connected to pwm 2 overflow C i12 connected to eeprom exit from halt mode may only be triggered by an external interrupt on one of the following ports: pa0-pa7 (i0), pb0-pb1 (i0), or by an internal in- terrupt coming from can peripheral (i1). if more than one input pin of a group connected to the same interrupt line are selected simultaneous- ly, the or of this signals generates the interrupt. table 4. interrupt mapping interrupts register flag name interrupt source vector address reset n/a n/a - fffeh-ffffh software n/a n/a - fffch-fffdh ext. interrupt (ports pa0-pa7, pb0-pb1) n/a n/a i0 fffah-fffbh receive interrupt flag can status rxifi i1 fff8h-fff9h transmit interrupt flag txif error interrupt pending epnd power bridge short circuit bridge control status sc i2 fff6h-fff7h overtemperature ovt output compare 1 timer 1 status ocf1_1 i3 fff4h-fff5h output compare 2 ocf2_1 input capture 1 timer 1 status icf1_1 i4 fff2h-fff3h input capture 2 icf2_1 timer overflow timer 1 status tof_1 i5 fff0h-fff1h output compare 1 timer 2 status ocf1_2 i6 ffeeh-ffefh output compare 2 ocf2_2 input capture 1 timer 2 status icf1_2 i7 ffech-ffedh input capture 2 icf2_2 timer overflow timer 2 status tof_2 i8 ffeah-ffebh adc end of conversion adc control eoc i9 ffe8h-ffe9h pwm 1 overflow n/a n/a i10 ffe6h-ffe7h pwm 2 overflow n/a n/a i11 ffe4h-ffe5h eeprom programming eeprom control e2ite i12 ffe2h-ffe3h 23/103 L9805 interrupts (contd) figure 11. interrupt processing flowchart note 1. see table 4 interrupt trap fetch next instruction of appropriate interrupt service routine execute instruction push pc,x,a,cc set i bit to 1 vr01172b n y load pc with appropriate interrupt vector ( 1) i bit = 1 n y onto stack 24/103 L9805 3.7 power saving modes 3.7.1 introduction there are three power saving modes. the slow mode may be selected by setting the relevant bits in the miscellaneous register as detailed in section 3.4 . wait and halt modes may be entered using the wfi and halt instructions. 3.7.2 slow mode in slow mode, the oscillator frequency can be di- vided by 4, 8, 16 or 32 rather than by 2. the cpu and peripherals (except can, see note) are clocked at this lower frequency. slow mode is used to reduce power consumption. note: before entering slow mode and to guaran- tee low power operations, the can controller must be placed by software in standby mode. 3.7.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. all peripher- als remain active. during wait mode, the i bit (cc register) is cleared, so as to enable all interrupts. all other registers and memory remain un- changed. the mcu will remain in wait mode until an interrupt or reset occurs, whereupon the pro- gram counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt (coming from can, timers 1 & 2, eeprom, adc, pwm 1 & 2, i/o ports peripherals and power bridge) occurs, causing its wake-up. refer to figure 12 below. figure 12. wait mode flow chart wait instruction reset fetch reset vector or service interrupt interrupt y n n y cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit on on cleared off 25/103 L9805 power saving modes (contd) 3.7.4 halt mode the halt mode is the mcu lowest power con- sumption mode. the halt mode is entered by exe- cuting the halt instruction. the internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. when entering halt mode, the i bit in the cc reg- ister is cleared so as to enable external interrupts. if an interrupt occurs, the cpu becomes active. the mcu can exit the halt mode upon reception of either an external interrupt (i0), a internal interrupt coming from the can peripheral (i1) or a reset. the oscillator is then turned on and a stabilisation time is provided before releasing cpu operation. the stabilisation time is 4096 cpu clock cycles. after the start up delay, the cpu continues opera- tion by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. note the halt mode cannot be used when the watchdog or the safeguard are enabled, if the halt instruction is executed while the watchdog or safeguard system are enabled, a reset is auto- matically generated thus resetting the entire mcu. note halt mode affects only the digital section of the device. all the analog circuit remain in their status, including adc, voltage regulators, bus transceivers and power bridge. figure 13. halt mode flow chart n n external interrupt reset halt instruction 4096 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y 26/103 L9805 4 voltage regulator 4.1 introduction the on chip voltage regulator provides two regu- lated voltage, nominally 5v both. vcc supplies adc and the analog periphery and vdd supplies the microcontroller and logic parts. these voltage are available at pins vdd and vcc to supply ex- ternal components and connects a capacitors to optimize emi performance. a pre-regulator circuit allows to connect external tantalum capacitors to a lower (10v) voltage (vb2 pin). 4.1.1 functional description the main supply voltage is taken from vb1 pin. a voltage pre-regulator provides the regulated volt- age on pin vb2. vb2 is the supply for the digital and analog regulators. the block diagram shows the connections between the regulators and the external pins. in order to prevent negative spikes on the battery line to propagate on the internal supply generating spurious reset, a series diode supply vb1 pin is recommended. figure 14. voltage regulation block diagram 4.2 digital section power supply the digital supply voltage vdd is available at pin number 42 and 9. the digital ground gnd is avail- able at pin number 43 and 12. pin 42 and 43 are the actual voltage regulator out- put and external loads must be supply by these pin. the 100nf compensation capacitor should be connected as close as possible to pin 42 and 43. pin number 9 and 12 provide an external access to the internal oscillator supply. resonators capaci- tors should be grounded on pin 12. adc pre-regulator vb1 vb2 force analog voltage regulator sense vcc agnd digital voltage regulator vdd(42) gnd(43) battery 27/103 L9805 the application board can improve noise reduction in the chip connecting directly pin 42 to pin 9 and pin 43 to pin 12 using traces as short as possible. an additional capacitor mounted close to pin 9 and 12 can lead additional improvement. 4.2.1 vdd short circuit protection the output current of the digital voltage regulator is controlled by a circuit that limits it to a maximum value (i maxvdd ). when the output current exceeds this value the vdd voltage starts falling down. ex- ternal loads must be chosen taking in account this maximum current capability of the regulator. 4.3 analog section power supply the analog supply voltage is available on vcc pin. the external 100nf compensation capacitor should be placed as close as possible to this pin and agnd pin. vcc is the reference voltage for the ad conver- sion and must be used to supply ratiometric sen- sors feeding ad inputs. any voltage drop between vcc pin and the sensor supply pin on the applica- tion board, will cause the adc to be inaccurate when reading the sensors output. 4.3.1 vcc short circuit protection the output current of the analog voltage regulator is controlled by a circuit that limits it to a maximum value (i maxvcc ). when the output current exceeds this value the vcc voltage starts falling down. ex- ternal loads must be chosen taking in account this maximum current capability of the regulator. warning: the pin vb2 is not short circuit pro- tected so a short circuit on this pin will destroy the device. 28/103 L9805 5 on-chip peripherals 5.1 i/o ports 5.1.1 introduction the internal i/o ports allow the transfer of data through digital inputs and outputs, the interrupt generation coming from an i/o and for specific pins, the input/output of alternate signals for the on-chip peripherals (timers...). each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 5.1.2 functional description each i/o pin may be programmed independently as a digital input or a digital output, using the cor- responding register bits. each port pin of the i/o ports can be individually configured under software control as either input or output. each bit of a data direction register (ddr) corre- sponds to an i/o pin of the associated port. this corresponding bit must be set to configure its as- sociated pin as output and must be cleared to con- figure its associated pin as input. the data direc- tion registers can be read and written. 5.1.2.1 input mode when ddr=0, the corresponding i/o is configured in input mode. in this case, the output buffer is switched off, the state of the i/o is readable through the data reg- ister address, but the i/o state comes directly from the schmitt-trigger output and not from the data register output. 5.1.2.2 interrupt function when an i/o is configured in input with interrupt generation mode (ddr=0 and or=1), a low level or any transition on this i/o (according to the mis- cellaneous register configuration - see section 3.4 , b3, b4 external interrupt option) will gener- ate an interrupt request to the cpu. each pin can independently generate an interrupt request. when at least one of the interrupt inputs is tied low, the ports common interrupt will activate a cpu interrupt input according to the external in- terrupt option in the miscellaneous register. 5.1.2.3 output mode when ddr=1, the corresponding i/o is configured in output mode. in this mode, the interrupt function is disabled. the output buffers can be individually configured as open drain or push-pull by means of the op- tion register. the output buffer is activated according to the data registers content. a read operation is directly performed from the data register output. 5.1.2.4 alternate function a signal coming from a on-chip peripheral can be output on the i/o. in this case, the i/o is automatically configured in output mode (without pull-up). this must be controlled directly by the peripheral with a signal coming from the peripheral which en- ables the alternate signal to be output. the i/os state is readable as in normal mode by addressing the corresponding i/o data register. a signal coming from an i/o can be input in a on- chip peripheral. before using an i/o as alternate input, it must be configured in input without interrupt mode (ddr=0 and or=0). so, both alternate input configuration (with or without pull-up) and i/o input configuration (with or without pull-up) are the same. the signal to be input in the peripheral is taken af- ter the schmitt-trigger. the i/os state is readable as in normal mode by addressing the correspond- ing i/o data register. 29/103 L9805 i/o ports (contd) 5.1.2.5 i/o port implementation the i/o port register configurations are resumed as following. port pa(7:0), port pb(2:0) reset status: dr=0, ddr=0 and or=0 (input mode, no interrupt). these ports offer interrupt capabilities. 5.1.2.6 dedicated configurations table 5. port a configuration table 6. port b configuration ddr or mode 00 input no interrupt (pull-up enabled) 01 input interrupt (pull-up enabled) 1 0 open-drain output 1 1 push-pull output port a i / o function input output alternate interrupt pa0 triggered with pull-up push-pull/open drain ocmp2_1: output compare #2 timer 1 wake-up interrupt (i0) pa1 triggered with pull-up push-pull/open drain ocmp1_1: output compare #1 timer 1 wake-up interrupt (i0) pa2 triggered with pull-up push-pull/open drain icap2_1: input capture #2 timer 1 wake-up interrupt (i0) pa3 triggered with pull-up push-pull/open drain icap1_1: input capture #1 timer 1 wake-up interrupt (i0) pa4 triggered with pull-up push-pull/open drain extclk_1: external clock timer 1 wake-up interrupt (i0) pa5 triggered with pull-up push-pull/open drain ocmp2_2: output compare #2 timer 2 wake-up interrupt (i0) pa6 triggered with pull-up push-pull/open drain ocmp1_2: output compare #1 timer 2 wake-up interrupt (i0) pa7 triggered with pull-up push-pull/open drain icap2_2: input capture #2 timer 2 wake-up interrupt (i0) port b i / o function input output alternate interrupt pb0 triggered with pull-up push-pull/open drain icap1_2: input capture #1 timer 2 wake-up interrupt (i0) pb1 triggered with pull-up push-pull/open drain extclk_2: external clock timer 2 wake-up interrupt (i0) pb2 1) note 1. the pb2 bit is not connected to the external. it must be configured as an input without interrupt, to be used only as an alternate function. not connected to pad not connected to pad pwmi: pwm input 30/103 L9805 i/o ports (contd) figure 15 . ports pa0-pa7, pb0-pb1 i dr ddr latch latch data bus dr sel ddr sel vdd pa d m u x alternate alternate digital enable alternate enable alternate m u x alternate input output p-buffer n-buffer 1 0 1 0 or latch or sel from other bits interrupt pull-up condition enable enable gnd 31/103 L9805 i/o ports (contd) 5.1.3 register description 5.1.3.1 data registers (padr) port a: 0000h read/write reset value: 0000 0000 (00h) (pbdr) port b: 0004h read/write reset value: 0000 0000 (00h) 5.1.3.2 data direction registers (paddr) port a: 0001h read/write reset value: 0000 0000 (00h) (input mode) (pbddr) port b: 0005h read/write reset value: 0000 0000 (00h) (input mode) 5.1.3.3 option registers (paor) port a: 0002h read/write reset value: 0000 0000 (00h) (no interrupt) (pbor) port b: 0006h read/write reset value: 0000 0000 (00h) (no interrupt) 70 msb lsb 70 msb 0 0 0 0 lsb 70 msb lsb 70 msb 0 0 0 0 lsb 70 msb lsb 70 msb 0 0 0 0 lsb 32/103 L9805 5.2 16-bit timer 5.2.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. 5.2.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n input capture functions with C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports the block diagram is shown in figure 16, on page 33. note: some external pins are not available on all devices. refer to the device pin out description. 5.2.3 functional description 5.2.3.1 counter the principal block of the programmable timer is a 16-bit free running counter and its associated 16-bit registers: counter registers C counter high register (chr) is the most sig- nificant byte (msb). C counter low register (clr) is the least sig- nificant byte (lsb). alternate counter registers C alternate counter high register (achr) is the most significant byte (msb). C alternate counter low register (aclr) is the least significant byte (lsb). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (overflow flag), (see note page 3). writing in the clr register or aclr register resets the free running counter to the fffch value. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 7 clock control bits . the value in the counter register re- peats every 131.072, 262.144 or 524.288 internal processor clock cycles depending on the cc1 and cc0 bits. 33/103 L9805 16-bit timer (contd) figure 16. timer block diagram mcu-peripheral interface counter alternate register output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 exclk cpu clock timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 cr1 cr2 sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc1 cc0 16 bit free running counter 34/103 L9805 16-bit timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the msb first, then the lsb value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the lsb of the count value at the time of the read. an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1register is set and C i bit of the ccr register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done by: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. this feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 5.2.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit determines the type of level transition on the external clock pin exclk that will trigger the free running counter. the counter is synchronised with the falling edge of the internal cpu clock. at least four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock frequen- cy must be less than a quarter of the cpu clock frequency. lsb is buffered read msb at t0 read lsb returns the buffered lsb value at t0 at t0 + d t other instructions beginning of the sequence sequence completed 35/103 L9805 16-bit timer (contd) figure 17. counter timing diagram, internal clock divided by 2 figure 18. counter timing diagram, internal clock divided by 4 figure 19. counter timing diagram, internal clock divided by 8 cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register overflow flag tof fffc fffd 0000 0001 cpu clock internal reset timer clock counter register overflow flag tof cpu clock internal reset timer clock counter register overflow flag tof fffc fffd 0000 36/103 L9805 16-bit timer (contd) 5.2.3.3 input capture in this section, the index, i , may be 1 or 2 the two input capture 16-bit registers (icr1 and icr2) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). icr i register is a read-only register. the active transition is software programmable through the iedg i bit of the control register (cr i ). timing resolution is one count of the free running counter: ( f cpu/(cc1.cc0) ). procedure to use the input capture function select the follow- ing in the cr2 register: C select the timer clock (cc1-cc0) (see table 7 clock control bits ). C select the edge of the active transition on the icap2 pin with the iedg2 bit. and select the following in the cr1 register: C set the icie bit to generate an interrupt after an input capture. C select the edge of the active transition on the icap1 pin with the iedg1 bit. when an input capture occurs: C icf i bit is set. C the icr i register contains the value of the free running counter on the active transition on the icap i pin (see figure 21 ). C a timer interrupt is generated if the icie bit is set and the i bit is cleared in the ccr register. oth- erwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request is done by: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the iclr i register. note: after reading the ichr i register, transfer of input capture data is inhibited until the iclr i regis- ter is also read. the icr i register always contains the free running counter value which corresponds to the most re- cent input capture. during halt mode, if at least one valid input cap- ture edge occurs on the icap i pin, the input cap- ture detection circuitry is armed. this does not set any timer flags, and does not wake-up the mcu. if the mcu is awoken by an interrupt, the input capture flag will become active, and data corre- sponding to the first valid edge during halt mode will be present. ms byte ls byte icr i ichr i iclr i 37/103 L9805 16-bit timer (contd) figure 20. input capture block diagram figure 21. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit icr1 icr2 edge detect circuit1 ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge. 38/103 L9805 16-bit timer (contd) 5.2.3.4 output compare in this section, the index, i , may be 1 or 2. this function can be used to control an output waveform or indicating when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the ocie bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (ocr1) and output compare register 2 (ocr2) contain the value to be compared to the free run- ning counter each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the ocri value to 8000h. timing resolution is one count of the free running counter: ( f cpu/(cc1.cc0) ). procedure to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i function. C select the timer clock (cc1-cc0) (see table 7 clock control bits ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie bit to generate an interrupt if it is needed. when match is found: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset and stays low until valid compares change it to a high level). C a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the ccr register (ccr). clearing the output compare interrupt request is done by: 3. reading the sr register while the ocf i bit is set. 4. an access (read or write) to the oclr i register. note: after a processor write cycle to the ochr i register, the output compare function is inhibited until the oclr i register is also written. if the oc i e bit is not set, the ocmp i pin is a gen- eral i/o port and the olvl i bit will not appear when match is found but an interrupt could be gen- erated if the ocie bit is set. the value in the 16-bit ocr i register and the olv i bit should be changed after each successful com- parison in order to control an output waveform or establish a new elapsed timeout. the ocr i register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = desired output compare period (in seconds calculated from the current counter) f cpu = internal clock frequency (see miscel- laneous register) cc1-cc0 = timer clock prescaler the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the ocr i register: C write to the ochr i register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oclr i register (enables the output compare function and clears the ocf i bit). ms byte ls byte ocr i ochr i oclr i d ocr i register value = t * f cpu (cc1.cc0) 39/103 L9805 16-bit timer (contd) figure 22. output compare block diagram figure 23. output compare timing diagram, internal clock divided by 2 output compare 16-bit circuit ocr1 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 ocr2 internal cpu clock timer clock counter output compare register compare register latch ocfi and ocmpi pin (olvli=1) cpu writes ffff ffff fffd fffd fffe ffff 0000 fffc 40/103 L9805 16-bit timer (contd) 5.2.3.5 forced compare mode in this section i may represent 1 or 2. the main purpose of the forced compare mode is to easily generate a fixed frequency. the following bits of the cr1 register are used: when the folv i bit is set, the olvl i bit is copied to the ocmp i pin. to provide this capability, internal logic allows a single instruction to change the olvl i bit and causes a forced compare with the new value of the olvl i bit. the ocf i bit is not set, and thus no interrupt re- quest is generated. 5.2.3.6 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode, select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit . C set oc1e pin, the ocmp1 pin is then dedicated to the output compare 1 function. and select the following in the cr2 register: C set the opm bit. C select the timer clock cc1-cc0 (see table 7 clock control bits ). load the ocr1 register with the value corre- sponding to the length of the pulse (see the formu- la in section 5.2.3.7 ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin. when the value of the counter is equal to the value of the contents of the ocr1 register, the olvl1 bit is output on the ocmp1 pin, (see figure 24 ). note: the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. the icf1 bit is set when an active edge occurs and can generate an interrupt if the icie bit is set. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 24. one pulse mode timing folv 2 folv 1 olvl 2 olvl 1 event occurs counter is initialized to fffch ocmp1 = olvl2 counter = ocr1 ocmp1 = olvl1 when when on icap1 one pulse mode cycle counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, ocr1=2ed0h, olvl1=0, olvl2=1 41/103 L9805 16-bit timer (contd) 5.2.3.7 pulse width modulation mode pulse width modulation mode enables the gener- ation of a signal with a frequency and pulse length determined by the value of the ocr1 and ocr2 registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the ocr2 register. procedure to use pulse width modulation mode select the fol- lowing in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful com- parison with ocr1 register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful com- parison with ocr2 register. C set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. and select the following in the cr2 register: C set the pwm bit. C select the timer clock (cc1-cc0) (see table 7 clock control bits ). load the ocr2 register with the value corre- sponding to the period of the signal. load the ocr1 register with the value corre- sponding to the length of the pulse if (olvl1=0 and olvl2=1). if olvl1=1 and olvl2=0 the length of the pulse is the difference between the ocr2 and ocr1 registers. the ocr i register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: C t = desired output compare period (seconds) Cf cpu = internal clock frequency (see miscella- neous register) C cc1-cc0 = timer clock prescaler the output compare 2 event causes the counter to be initialized to fffch (see figure 25, on page 42). note: after a write instruction to the ochr i regis- ter, the output compare function is inhibited until the oclr i register is also written. the ocf1 and ocf2 bits cannot be set by hard- ware in pwm mode therefore the output compare interrupt is inhibited. the input capture interrupt is available. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. ocr i value = t * f cpu (cc1.cc0) - 5 counter counter is reset to fffch ocmp1 = olvl2 counter = ocr2 ocmp1 = olvl1 when when = ocr1 pulse width modulation cycle 42/103 L9805 figure 25. pulse width modulation mode timing counter 34e2 fffc fffd fffe 2ed0 2ed1 2ed2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: ocr1=2ed0h, ocr2=34e2, olvl1=0, olvl2= 1 43/103 L9805 16-bit timer (contd) 5.2.4 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) timer1 register address: 0032h timer2 register address: 0042h read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bits of the sr register are set bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bits of the sr register are set bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. 0: no effect. 1: forces the olvl2 bit to be copied to the ocmp2 pin. bit 3 = folv1 forced output compare 1. 0: no effect. 1: forces olvl1 to be copied to the ocmp1 pin. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the ocr2 reg- ister. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the ocr1 register. 70 icie ocie toie folv 2 folv 1 olvl 2 iedg 1 olvl 1 44/103 L9805 16-bit timer (contd) control register 2 (cr2) timer1 register address: 0031h timer2 register address: 0041h read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 enable. 0: output compare 1 function is enabled, but the ocmp1 pin is a general i/o. 1: output compare 1 function is enabled, the ocmp1 pin is dedicated to the output compare 1 capability of the timer. bit 6 = oc2e output compare 2 enable. 0: output compare 2 function is enabled, but the ocmp2 pin is a general i/o. 1: output compare 2 function is enabled, the ocmp2 pin is dedicated to the output compare 2 capability of the timer. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the ocr1 register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of ocr1 register; the period depends on the value of ocr2 regis- ter. bit 3, 2 = cc1-cc0 clock control. the value of the timer clock depends on these bits: table 7. clock control bits bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin exclk will trigger the free running counter. 0: a falling edge triggers the free running counter. 1: a rising edge triggers the free running counter. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg cc1 cc0 timer clock 00 f cpu / 4 01 f cpu / 2 10 f cpu / 8 11 external clock (where available) 45/103 L9805 16-bit timer (contd) status register (sr) timer1 register address: 0033h timer2 register address: 0043h read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value) 1: an input capture has occurred. to clear this bit, first read the sr register, then read or write the low byte of the icr1 (iclr1) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value) 1: the content of the free running counter has matched the content of the ocr1 register. to clear this bit, first read the sr register, then read or write the low byte of the ocr1 (oclr1) reg- ister. bit 5 = tof timer overflow. 0: no timer overflow (reset value) 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register do not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value) 1: an input capture has occurred.to clear this bit, first read the sr register, then read or write the low byte of the icr2 (iclr2) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value) 1: the content of the free running counter has matched the content of the ocr2 register. to clear this bit, first read the sr register, then read or write the low byte of the ocr2 (oclr2) reg- ister. bit 2-0 = unused. 70 icf1 ocf1 tof icf2 ocf2 46/103 L9805 16-bit timer (contd) input capture 1 high register (ichr1) timer1 register address: 0034h timer2 register address: 0044h read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (iclr1) timer1 register address: 0035h timer2 register address: 0045h read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (ochr1) timer1 register address: 0036h timer2 register address: 0046h read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oclr1) timer1 register address: 0037h timer2 register address: 0047h read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of output compare 2 high register (ochr2) timer1 register address: 003eh timer2 register address: 004eh read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oclr2) timer1 register address: 003fh timer2 register address: 004fh read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) timer1 register address: 0038h timer2 register address: 0048h read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 47/103 L9805 counter low register (clr) timer1 register address: 0039h timer2 register address: 0049h read/write reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit.16-bit alternate counter high register (achr) timer1 register address: 003ah timer2 register address: 004ah read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) timer1 register address: 003bh timer2 register address: 004bh read/write reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ichr2) timer1 register address: 003ch timer2 register address: 004ch read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (iclr2) timer1 register address: 003dh timer2 register address: 004dh read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 48/103 L9805 16-bit timer (contd) table 8. 16-bit timer register map and reset values address (hex.) register name 76543210 timer1: 32 timer2: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer1: 31 timer2: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer1: 33 timer2: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timer1: 34 timer2: 44 ichr1 reset value msb - ------ lsb - timer1: 35 timer2: 45 iclr1 reset value msb - ------ lsb - timer1: 36 timer2: 46 ochr1 reset value msb - ------ lsb - timer1: 37 timer2: 47 oclr1 reset value msb - ------ lsb - timer1: 3e timer2: 4e ochr2 reset value msb - ------ lsb - timer1: 3f timer2: 4f oclr2 reset value msb - ------ lsb - timer1: 38 timer2: 48 chr reset value msb 1111111 lsb 1 timer1: 39 timer2: 49 clr reset value msb 1111110 lsb 0 timer1: 3a timer2: 4a achr reset value msb 1111111 lsb 1 timer1: 3b timer2: 4b aclr reset value msb 1111110 lsb 0 timer1: 3c timer2: 4c ichr2 reset value msb - ------ lsb - timer1: 3d timer2: 4d iclr2 reset value msb - ------ lsb - 49/103 L9805 5.3 pwm generator 5.3.1 introduction this pwm peripheral includes a 16-bit pulse width modulator (pwm) and a programmable prescaler able to generate an internal clock with period as long as 128*t cpu . the repetition rate of the 16-bit pwm output can be defined by a dedicated register (f cpu /cyreg); its resolution is defined by the internal clock as per the prescaler programming. main features -programmable prescaler: f cpu divided by 2, 4, 8, 16, 32, 64 or 128. -1 control register -2 dedicated 16-bit registers for cycle and duty control -1 dedicated maskable interrupt procedure to use the pulse width modulation peripheral, the en_pwm bit in conreg register must be set. load ps(2:0) in conreg register to define the programmable prescaler. load the cyreg register with the value defining the cycle length (in internal clock periods). the 16 bits of this register are separated in two registers: cyregh and cyregl. load the dutyreg register with the value corre- sponding to the pulse length (in internal cycle peri- ods). the 16 bits of this register are separated in two registers: dutyregh and dutyregl. the counter is reset to zero when en_pwm bit is reset. writing the dutyreg and cyreg registers has no effect on the current pwm cycle. the cycle or duty cycle change take place only after the first overflow of the counter. the suggested procedures to change the pwm parameters are the following: duty cycle control: - write the low and high dutyreg registers. a writing only on one dutyreg register has no effect until both registers are written. the current pwm cycle w ill be completed. the new duty cycle will be effective at the following pwm cycle, with respect to the last dutyreg writing. cycle control: - write the low and high cyreg register a writing only on one cyreg register has no ef- fect until both registers are written. the current pwm cycle will be completed. the new cycle will be effective at the following pwm cycle, with respect to the last cyreg writing. another possible procedure is: - reset the en_pwm bit. - write the wanted configuration in cyreg and dutyreg.. - set the en_pwm bit. if the en_pwm bit is set after being reset, the cur- rent values of dutyreg and cyreg are deter- mining the output waveform, no matter if only the low or the high part, or both were written. the first time en_pwm is set, if cyreg and du- tyreg were not previously written, the output is permanently low, because the default value of the registers is 00h. changing the prescaler ratio writing ps(2:0) in conreg has immediate effect on the waveform frequency. 5.3.2 functional description the pwm module consists of a 16-bit counter, a comparator and the cycle generation logic. pwm generation the counter increments continuously, clocked at internal clock generated by prescaler. whenever the 16 bits of the counter (defined as the pwm counter) overflow, the output level is set. the over- flow value is defined by cyreg register. the state of the pwm counter is continuously compared to the pwm binary weight, as defined in dutyreg register, and when a match occurs the output level is reset. figure 26. pwm cycle note: if the cyreg value is minor or equal than dutyreg value, pwm output remains set. with a counter counter is reset out pwm = 1 counter = cyreg out pwm = 0 when when = dutyreg pulse width modulation cycle 50/103 L9805 dutyreg value of 0000h, the pwm output is per- manently at low level, no matter of the value of cyreg. with a dutyreg value of ffffh, the pwm output is permanently at high level. interrupt request the en_int bit in conreg register must be set to enable the interrupt generation. when the 16 bits of the counter roll-over cyclereg value, in- terrupt request is set. the interrupt request is cleared when any of the pwm registers is written. figure 27. pwm generation counter cyreg compare value 000 t pwm output t t (internal clock) x cyreg_value value interrupt generation 51/103 L9805 5.3.3 register description the pwm is associated with a 8-bit control regis- ters, and with two 16-bit data registers, each split in two 8-bit registers. pwm cycle register low (cyregl) pwm1 register address: 0011h pwm2 register address: 0019h read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be multiplied by internal clock period. pwm cycle register high (cyregh) pwm1 register address: 0010h pwm2 register address: 0018h read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the high part of the value to be multiplied by internal clock peri- od. pwm dutycycle register low (du- tyregl) pwm1 register address: 0013h pwm2 register address: 001bh read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value corresponding to the binary weight of the pwm pulse. pwm dutycycle register high (du- tyregh) pwm1 register address: 0012h pwm2 register address: 001ah read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the high part of the value corresponding to the binary weight of the pwm pulse . pwm control register (conreg) pwm1 register address: 0014h pwm2 register address: 001ch read/write reset value: 0000 0000 (00h) bit 0= en _pwm : 1 = enables the pwm output, 0 = disables pwm output. bit 1= en _int : 1 = enables interrupt request, 0 disables interrupt request. bit 4, 3, 2= ps2 , ps1 , ps0 : prescaler bits the value of the pwm internal clock depends on these bits. bit 5, 6, 7= not used. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 7 43210 0 0 0 ps2 ps1 ps0 en_ int en_ pwm ps2 ps1 ps0 pwm internal clock 000 f cpu 001 f cpu / 2 010 f cpu / 4 011 f cpu / 8 100 f cpu / 16 101 f cpu / 32 110 f cpu / 64 111 f cpu / 128 52/103 L9805 pwm counter register low (ctl) pwm1 register address: 0016h pwm2 register address: 001eh read only reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the pwm counter value. pwm counter register high(cth) pwm1 register address: 0015h pwm2 register address: 001dh read only reset value: 0000 0000 (00h) this is an 8-bit register that contains the high part of the pwm counter value. 70 msb lsb 70 msb lsb table 9. pwm timing (f cpu = 8mhz) prescaler (ps) t internal clock cyreg @16 bit resolution pwm cycle @ f in =8mhz 0 1/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 0.125 m s..... ~8192 m s 1 1/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 0.25 m s....... ~16384 m s 2 1/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 0.5 m s......... ~32768 m s 3 1/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 1 m s............ 65535 m s 4 1/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 2 m s............ 131070 m s 5 1/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 4 m s............ 262140 m s 6 1/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 8 m s............ 524280 m s 7 1/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 16 m s.......... 1048560 m s 53/103 L9805 figure 28. pwm block diagram data bus cyreg dutyreg conreg | . | . | . | ps1 | ps2 | ps3 | en_int | en_pwm | clock 7 6 5 4 3 2 1 3 16-bit counter comparator2 comparator1 logic irq pwm 16 16 2 m u x 54/103 L9805 5.4 pwm i/o 5.4.1 introduction the pwm i/o interface is a circuit able to connect internal logic circuits with external high voltage lines. the two interfaces represent respectively the re- ceiver and the transmitter section of a standard is0 9141 transceiver. connecting pwmo and pwmi together a stand- ard k bus (iso 9141) can be realized. voltage thresholds are referred to the battery volt- age connected to vbr pin. this pin must be used as reference for the k bus. voltage drops between this pin and the battery line can cause thresholds mismatch between the L9805 iso trasceiver and the counterpart trasceiver(s) connected to the same bus line. see figure 29 for a block diagram description of the two interfaces. figure 29. pwm i/o block diagram 5.4.2 pwmo pwmo is an output line, directly driven by the pwm2 output signal. the circuit translates the log- ic levels of pwm2 output to voltage levels referred to the vb supply (see figure 29 ). when pwm2=0 the open drain is switched off, in the other case the pwmo line is pulled down by the open drain driv- er. pwmo is protected against short circuit to battery by a dedicated circuit that limits the current sunk by the output transistor. when the limiter is activat- ed the voltage on pwmo pin rises up. if the limiter remains active for more than 25 m s the driver is switched off. if the battery or ground connection are lost, the pwmo line shows a controlled impedance charac- teristic (see figure 30 ). pwm0 is high at nreset is asserted. figure 30. impedance at pwmo/i pin 5.4.3 pwmi pwmi is an input line, directly connected to pb2 bit. the circuit translates the voltage levels re- ferred to vb voltage supply to the internal logic lev- els (see figure 29 ). when the voltage on pwmi vdd pwmo vdd timer capture input pwm2 output pb2 register bit - + pwmi vbr battery k bus 50k w 50k w 5 m a v k i k 14v 55/103 L9805 pin is higher than vb/2 pb2 reads an high logic level. if the bit pwmi in dcsr register is set (see sec- tion 3.2.1 ), pwmi is directly connected with the in- put capture 2 on timer 2, which is otherwise con- nected in alternate function to pa7 (see figure 31 ). an internal pull down current generator (5ua) al- lows to detect the open bus condition (external pull up missing). if the battery or ground connection are lost, the pwmi line shows a controlled impedance charac- teristic (see figure 30 ).. figure 31. pwmi function 0 1 timer 2 icap2 pien dcsr pwm i/o m u x pwm input pa(7) alternate input port pwmi pa7 pa(7) pb(2) .............. ..... 56/103 L9805 5.5 10-bit a/d converter (ad10) 5.5.1 introduction the analog to digital converter is a single 10-bit successive approximation converter with 4 input channels. analog voltage from external sources are input to the converter through ad2,ad3 and ad4 pins. channel 1 (ad1) is connected to the in- ternal temperature sensor (see section 5.5.5 ). note the anti aliasing filtering must be accom- plished using an external rc filter. the internal ad1 channel is filtered by an rc network with ap- prox. 1us time constant. 5.5.2 functional description the result of the conversion is stored in 2 regis- ters: the data register high (adcdrh) and the data register low (adcdrl). the a/d converter is enabled by setting the adst bit in adccsr register. bits ch1 and ch0 of ad- ccsr register select the channel to be convert- ed. the high and low reference voltage are con- nected to pins vcc and agnd. when enabled, the a/d converter performs a com- plete conversion in 14us (with system clock f cpu =8mhz). the total conversion time includes multiplex, sampling of the input voltage, 10-bit conversion and writing drh and drl registers. when the conversion is completed coco bit (conversion completed) is set in adccsr. a conversion starts from the moment adst bit is set. when a conversion is running it is possible to write the adccsr without stopping the adc oper- ations, because all the data in adccsr are latched when adst is set. this property allows to select a different channel to be processed during the next conversion or to manage the interrupt en- able bit. the new setting will have effect on the next conversion (including interrupt generation) at the end of the conversion adst is reset and coco bit is set. note to start a new conversion the adst must be set after the completion of the current one. any writing to adst when a conversion is running (coco=0) has no effect since adst bit is auto- matically reset by the end of conversion event. figure 32. block diagram of the analog to digital converter ch0 ch1 adst logic u x m d i v clk 8mhz 2 mhz start conversion ..... ad0 ad9 drh drl end conversion wr vin vcc agnd inputs csr sampling + conversion latch adie 57/103 L9805 5.5.3 input selections and sampling the input section of the adc includes the analog multiplexer and a buffer. the input of the buffer is permanently connected to the multiplexer output. the buffer output is fed to the sample and hold cir- cuit. the multiplexer is driven with ch1 and ch0 bit only after adst is set. starting from this event, the sampler follows the selected input signal for 2.5us and then holds it for the remaining conversion time (i.e. when the conversion is actually running). 5.5.4 interrupt management if adie bit is set in register adccsr, an interrupt is generated when a conversion is completed (i.e. when coco is set). the interrupt request is cleared when any of the adc registers is access (either read or write). enabling/disabling the interrupt generation while the conversion is running has no effect on the cur- rent conversion. adie value is latched when adst is set and this internal value holds all the conversion time long. 5.5.5 temperature sensing the ad1 input is internally connected to the output of a temperature sensing circuit. the sensor generates a voltage proportional to the absolute temperature of the die. it works over the whole temperature range, with a minimum resolu- tion of 1lsb/k (5mv/k) ( figure 33 shows the in- dicative voltage output of the sensor). note the voltage output of the sensor is only relat- ed to the absolute temperature of the silicon junc- tions. junction temperature and ambient tempera- ture must be related taking in account the power dissipated by the device and the thermal resist- ance rth je between the silicon and the environ- ment around the application board. figure 33. temperature sensor output the output of the sensor is not ratiometric with the voltage reference for the adc conversion (vcc). when calculating the adc reading error of this sig- nal the variation of vcc must be accounted. addi- tional errors are due to the intrinsic spread of the sensor characteristic. 5.5.6 precise temperature measurement to allow a more precise measurement of the tem- perature a trimming procedure can be adopted (on request). the temperature is measured in ews and two val- ues are stored in four eeprom bytes (see memo- ry map): t0l,t0h: temperature of the trimming measure- ment (in kelvin). vt0l,vt0h: output value of the adc correspond- ing to t0 (in number of lsbs). the corrected measurement of the temperature in kelvin must be accomplished in the following way: where vtemp is the output code in lsb of the adc corresponding to the measurement. example: if the value stored in eeprom are: 0c7ch: 01h ->t0h 0c7dh: 43h ->t0l 0c7eh: 01h -> vt0h 0c7fh: 5ch -> vt0l t0 = 0143h = 323k (50 celsius) vto = 015ch = 348 lsb (conversion of 1.7v, sen- sor output) and the sensor output is 2v, converted by the adc in code 0110011001 = 019ah = 410lsb, the tem- perature of the chip is temp = 019ah * 0143h / 015ch = 017ch equivalent to: temp = 410 * 323 / 348 = 380 k = 107 c note the sensor circuit may have two kind of er- ror: one translating its output characteristic up and down and the other changing its slope. the de- scribed trimming recovers only the translation er- rors but can not recover slope error. after trim- ming, being t trim the trimming temperature, the specified precision can be achieved in the range t trim -80, max[t trim +80, 150 c]. precision is re- lated to the read temperature in kelvin. v temp temperature (k) 1.0 2.5 1.3 1.6 1.9 2.2 273 323 373 423 473 223 max min temp (in k) = vtemp * t0 / vt0 58/103 L9805 5.5.7 register description control/status register (adccsr) address: 0072h read/write reset value: 0010 0000 (20h) bit 7,6 = reserved bit 5 = coco (read only) conversion complete coco is set (by the adc) as soon as a conver- sion is completed (results can be read). coco is cleared by setting adst=1 (start of new conver- sion). if coco=0 a conversion is running, if co- co=1 no conversion is running. bit 4 = adie a/d interrupt enable this bit is used to enable / disable the interrupt function: 0: interrupt disabled 1: interrupt enabled bit 3= reserved bit 2= adst start conversion when this bit is set a new conversion starts. adst is automatically reset when the conversion is com- pleted (coco=1). bits 1-0 = ch1-ch0 channel selection these bits select the analog input to convert. see table 10 for reference. table 10. adc channel selection table data register high (adcdrh) address: 0070h read only reset value: 00000 0000 (00h) bit 1:0 = ad9-ad8 analog converted value this register contains the high part of the convert- ed analog value data register low (adcdrl) address: 0071h read only reset value: 00000 0000 (00h) bit 7:0 = ad7-ad0 analog converted value this register contains the low part of the converted analog value 70 00 coco adie 0 adst ch1 ch0 ch1 ch0 channel 0 0 ad1, temperature sensor 0 1 ad2, external input 1 0 ad3, external input 1 1 ad4, external input 70 000000ad9ad8 70 ad7ad6ad5ad4ad3ad2ad1ad0 59/103 L9805 5.6 controller area network (can) 5.6.1 introduction this peripheral is designed to support serial data exchanges using a multi-master contention based priority scheme as described in can specification rev. 2.0 part a. it can also be connected to a 2.0 b network without problems, since extended frames are checked for correctness and acknowledged accordingly although such frames cannot be trans- mitted nor received. the same applies to overload frames which are recognized but never initiated. figure 34. can block diagram tx/rx buffer 1 10 bytes tx/rx buffer 2 10 bytes tx/rx buffer 3 10 bytes id filter 0 4 bytes id filter 1 4 bytes st7 interface psr icr isr brpr csr tecr recr can 2.0b passive core shreg bcdl crc btl rx tx eml st7 internal bus btr 60/103 L9805 controller area network (contd) 5.6.2 main features C support of can specification 2.0a and 2.0b pas- sive C three prioritized 10-byte transmit/receive mes- sage buffers C two programmable global 12-bit message ac- ceptance filters C programmable baud rates up to 1 mbit/s C buffer flip-flopping capability in transmission C maskable interrupts for transmit, receive (one per buffer), error and wake-up C automatic low-power mode after 20 recessive bits or on demand (stand-by mode) C interrupt-driven wake-up from stand-by mode upon reception of dominant pulse C optional dominant pulse transmission on leaving stand-by mode C automatic message queuing for transmission upon writing of data byte 7 C programmable loop-back mode for self-test op- eration C advanced error detection and diagnosis func- tions C software-efficient buffer mapping at a unique ad- dress space C scalable architecture. 5.6.3 functional description 5.6.3.1 frame formats a summary of all the can frame formats is given in figure 35 for reference. it covers only the stand- ard frame format since the extended one is only acknowledged. a message begins with a start bit called start of frame (sof). this bit is followed by the arbitration field which contains the 11-bit identifier (id) and the remote transmission request bit (rtr). the rtr bit indicates whether it is a data frame or a re- mote request frame. a remote request frame does not have any data byte. the control field contains the identifier extension bit (ide), which indicates standard or extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes (dlc). the data field ranges from zero to eight bytes and is followed by the cyclic redundancy check (crc) used as a frame integrity check for detecting bit errors. the acknowledgement (ack) field comprises the ack slot and the ack delimiter. the bit in the ack slot is placed on the bus by the transmitter as a re- cessive bit (logical 1). it is overwritten as a domi- nant bit (logical 0) by those receivers which have at this time received the data correctly. in this way, the transmitting node can be assured that at least one receiver has correctly received its message. note that messages are acknowledged by the re- ceivers regardless of the outcome of the accept- ance test. the end of the message is indicated by the end of frame (eof). the intermission field defines the minimum number of bit periods separating con- secutive messages. if there is no subsequent bus access by any station, the bus remains idle. 5.6.3.2 hardware blocks the can controller contains the following func- tional blocks (refer to figure 34 ): C st7 interface: buffering of the st7 internal bus and address decoding of the can registers. C tx/rx buffers: three 10-byte buffers for trans- mission and reception of maximum length mes- sages. C id filters: two 12-bit compare and dont care masks for message acceptance filtering. C psr: page selection register (see memory map). C brpr: clock divider for different data rates. C btr: bit timing register. C icr: interrupt control register. C isr: interrupt status register. C csr: general purpose control/status register. C tecr: transmit error counter register. C recr: receive error counter register. C btl: bit timing logic providing programmable bit sampling and bit clock generation for synchroni- zation of the controller. C bcdl: bit coding logic generating a nrz-coded data-stream with stuff bits. C shreg: 8-bit shift register for serialization of data to be transmitted and parallelisation of re- ceived data. C crc: 15-bit crc calculator and checker. C eml: error detection and management logic. C can core: can 2.0b passive protocol control- ler. 61/103 L9805 figure 35. can frames data field 8 * n control field 6 arbitration field 12 crc field 16 ack field 7 sof id dlc crc data frame 44 + 8 * n arbitration field 12 rtr ide r0 sof id dlc remote frame 44 crc field 16 7 crc control field 6 overload flag 6 overload delimiter 8 overload frame error flag 6 error delimiter 8 error frame flag echo 6 bus idle inter-frame space suspend 8 intermission 3 transmission ack ack 2 2 inter-frame space or overload frame inter-frame space inter-frame space or overload frame inter-frame space inter-frame space or overload frame data frame or remote frame notes: ? 0 <= n <= 8 ? sof = start of frame ? id = identifier ? rtr = remote transmission request ? ide = identifier extension bit ? r0 = reserved bit ? dlc = data length code ? crc = cyclic redundancy code ? error flag: 6 dominant bits if node is error active else 6 recessive bits. ? suspend transmission: applies to error passive nodes only. ? eof = end of frame ? ack = acknowledge bit data frame or remote frame any frame inter-frame space or error frame end of frame or error delimiter or overload delimiter ack field end of frame rtr ide r0 eof 62/103 L9805 controller area network (contd) 5.6.3.3 modes of operation the can core unit assumes one of the seven states described below: C standby . stand-by mode is entered either on a chip reset or on resetting the run bit in the control/status register (csr). any on-going transmission or reception operation is not inter- rupted and completes normally before the bit time logic and the clock prescaler are turned off for minimum power consumption. this state is signalled by the run bit being read-back as 0. once in stand-by, the only event monitored is the reception of a dominant bit which causes a wake- up interrupt if the scie bit of the interrupt control register (icr) is set. the standby mode is left by setting the run bit. if the wkps bit is set in the csr register, then the controller passes through wake-up otherwise it enters resync directly. it is important to note that the wake-up mecha- nism is software-driven and therefore carries a significant time overhead. all messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored. C wake-up . the can bus line is forced to domi- nant for one bit time signalling the wake-up con- dition to all other bus members. figure 36. can controller state diagram n n n n n n n standby resync wake-up reception transmission error idle areset run run & wkps run & wkps fsyn & boff & 11 recessive bits | (fsyn | boff) & 128 * 11 recessive bits run write to data7 | tx error & nrtx start of frame arbitration lost tx error rx error tx ok rx ok boff boff 63/103 L9805 controller area network (contd) C resync . the re-synchronization mode is used to find the correct entry point for starting trans- mission or reception after the node has gone asynchronous either by going into the standby or bus-off states. re-synchronization is achieved when 128 se- quences of 11 recessive bits have been moni- tored unless the node is not bus-off and the fsyn bit in the csr register is set in which case a single sequence of 11 recessive bits needs to be monitored. C idle . the can controller looks for one of the fol- lowing events: the run bit is reset, a start of frame appears on the can bus or the data7 register of the currently active page is written to. C transmission . once the lock bit of a buffer control/status register (bcsrx) has been set and read back as such, a transmit job can be submitted by writing to the data7 register. the message with the highest priority will be transmit- ted as soon as the can bus becomes idle. among those messages with a pending trans- mission request, the highest priority is given to buffer 3 then 2 and 1. if the transmission fails due to a lost arbitration or to an error while the nrtx bit of the csr register is reset, then a new trans- mission attempt is performed. this goes on until the transmission ends successfully or until the job is cancelled by unlocking the buffer, by set- ting the nrtx bit or if the node ever enters bus- off or if a higher priority message becomes pend- ing. the rdy bit in the bcsrx register, which was set since the job was submitted, gets reset. when a transmission is in progress, the busy bit in the bcsrx register is set. if it ends successful- ly then the txif bit in the interrupt status regis- ter (isr) is set, else the teif bit is set. an interrupt is generated in either case provided the txie and teie bits of the icr register are set. the etx bit in the same register is used to get an early transmit interrupt and to automatically un- lock the transmitting buffer upon successful com- pletion of its job. this enables the cpu to get a new transmit job pending by the end of the cur- rent transmission while always leaving two buff- ers available for reception. an uninterrupted stream of messages may be transmitted in this way at no overrun risk. note: setting the srte bit of the csr register allows transmitted messages to be simultane- ously received when they pass the acceptance filtering. this is particularly useful for checking the integrity of the communication path. C reception . once the can controller has syn- chronized itself onto the bus activity, it is ready for reception of new messages. every incoming message gets its identifier compared to the ac- ceptance filters. if the bit-wise comparison of the selected bits ends up with a match for at least one of the filters then that message is elected for reception and a target buffer is searched for. this buffer will be the first one - order is 1 to 3 - that has the lock and rdy bits of its bcsrx regis- ter reset. C when no such buffer exists then an overrun interrupt is generated if the orie bit of the icr register has been set. in this case the identifi- er of the last message is made available in the last identifier register (lidhr and lidlr) at least until it gets overwritten by a new identifi- er picked-up from the bus. C when a buffer does exist, the accepted mes- sage gets written into it, the acc bit in the bcsrx register gets the number of the match- ing filter, the rdy and rxif bits get set and an interrupt is generated if the rxie bit in the isr register is set. up to three messages can be automatically received without intervention from the cpu because each buffer has its own set of status bits, greatly reducing the reactiveness require- ments in the processing of the receive inter- rupts. 64/103 L9805 C error . the error management as described in the can protocol is completely handled by hard- ware using 2 error counters which get increment- ed or decremented according to the error condition. both of them may be read by the appli- cation to determine the stability of the network. moreover, as one of the node status bits (epsv or boff of the csr register) changes, an inter- rupt is generated if the scie bit is set in the icr register. refer to figure 37 . figure 37. can error state diagram error passive when tecr or recr > 127, the epsv bit gets set when tecr and recr < 128, and the epsv bit gets cleared error active bus off when tecr > 255 the boff bit gets set when 128 * 11 recessive bits occur: - the boff bit gets cleared - the tecr register gets cleared - the recr register gets cleared the epsv bit gets cleared 65/103 L9805 controller area network (contd) 5.6.3.4 bit timing logic the bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and re- synchronization on following edges. its operation may be explained simply when the nominal bit time is divided into three segments as follows: C synchronisation segment (sync_seg) : a bit change is expected to lie within this time seg- ment. it has a fixed length of one time quanta (1 x t can ). C bit segment 1 (bs1) : defines the location of the sample point. it includes the prop_seg and phase_seg1 of the can st andard. its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compen- sate for positive phase drifts due to differences in the frequency of the various nodes of the net- work. C bit segment 2 (bs2) : defines the location of the transmit point. it represents the phase_seg2 of the can standard. its duration is programma- ble between 1 and 8 time quanta but may also be automatically shortened to compensate for neg- ative phase drifts. the resynchronization jump width (rjw) defines an upper bound to the amount of lengthening or shortening of the bit segments. it is programmable between 1 and 4 time quanta. a valid edge is defined as the first transition in a bit time from dominant to recessive bus level provid- ed the controller itself does not send a recessive bit. if a valid edge is detected in bs1 instead of sync_seg, bs1 is extended by up to rjw so that the sample point is delayed. conversely, if a valid edge is detected in bs2 in- stead of sync_seg, bs2 is shortened by up to rjw so that the transmit point is moved earlier. as a safeguard against programming errors, the configuration of the bit timing register (btr) is only possible while the device is in standby mode. figure 1. bit timing sync_seg bit segment 1 (bs1) bit segment 2 (bs2) nominal bit time 1 x t can t bs1 t bs2 sample point transmit point 66/103 L9805 controller area network (contd) 5.6.4 register description the can registers are organized as 6 general pur- pose registers plus 5 pages of 16 registers span- ning the same address space and primarily used for message and filter storage. the page actually selected is defined by the content of the page se- lection register. refer to figure 38 . 5.6.4.1 general purpose registers interrupt status register (isr) address: 005ah - read/write reset value: 00h bit 7 = rxif3 receive interrupt flag for buffer 3 - read/clear set by hardware to signal that a new error-free mes- sage is available in buffer 3. cleared by software to release buffer 3. also cleared by resetting bit rdy of bcsr3. bit 6 = rxif2 receive interrupt flag for buffer 2 - read/clear set by hardware to signal that a new error-free message is available in buffer 2. cleared by software to release buffer 2. also cleared by resetting bit rdy of bcsr2. bit 5 = rxif1 receive interrupt flag for buffer 1 - read/clear set by hardware to signal that a new error-free mes- sage is available in buffer 1. cleared by software to release buffer 1. also cleared by resetting bit rdy of bcsr1. bit 4 = txif transmit interrupt flag - read/clear set by hardware to signal that the highest priority message queued for transmission has been suc- cessfully transmitted (etx = 0) or that it has passed successfully the arbitration (etx = 1). cleared by software. bit 3 = scif status change interrupt flag - read/clear set by hardware to signal the reception of a domi- nant bit while in standby or a change from error ac- tive to error passive and bus-off while in run. also signals any receive error when esci = 1. cleared by software. bit 2 = orif overrun interrupt flag - read/clear set by hardware to signal that a message could not be stored because no receive buffer was available. cleared by software. bit 1 = teif transmit error interrupt flag - read/clear set by hardware to signal that an error occurred dur- ing the transmission of the highest priority message queued for transmission. cleared by software. bit 0 = epnd error interrupt pending - read only set by hardware when at least one of the three error interrupt flags scif, orif or teif is set. reset by hardware when all error interrupt flags have been cleared. caution ; interrupt flags are reset by writing a "0" to the cor- responding bit position. the appropriate way con- sists in writing an immediate mask or the ones com- plement of the register content initially read by the interrupt handler. bit manipulation instruction bres should never be used due to its read-modify- write nature. 70 rxif3 rxif2 rxif1 txif scif orif teif epnd 67/103 L9805 controller area network (contd) interrupt control register (icr) address: 005bh - read/write reset value: 00h bit 6 = esci extended status change interrupt - read/set/clear set by software to specify that scif is to be set on receive errors also. cleared by software to set scif only on status changes and wake-up but not on all receive errors. bit 5 = rxie receive interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message has been received free of er- rors. cleared by software to disable receive interrupt re- quests. bit 4 = txie transmit interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message has been successfully trans- mitted. cleared by software to disable transmit interrupt requests. bit 3 = scie status change interrupt enable - read/set/clear set by software to enable an interrupt request whenever the nodes status changes in run mode or whenever a dominant pulse is received in standby mode. cleared by software to disable status change inter- rupt requests. bit 2 = orie overrun interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message should be stored and no re- ceive buffer is avalaible. cleared by software to disable overrun interrupt re- quests. bit 1 = teie transmit error interrupt enable - read/set/clear set by software to enable an interrupt whenever an error has been detected during transmission of a message. cleared by software to disable transmit error inter- rupts. bit 0 = etx early transmit interrupt - read/set/clear set by software to request the transmit interrupt to occur as soon as the arbitration phase has been passed successfully. cleared by software to request the transmit inter- rupt to occur at the completion of the transfer. 70 0 esci rxie txie scie orie teie etx 68/103 L9805 controller area network (contd) control/status register (csr) address: 005ch - read/write reset value: 00h bit 6 = boff bus-off state - read only set by hardware to indicate that the node is in bus- off state, i.e. the transmit error counter exceeds 255. reset by hardware to indicate that the node is in- volved in bus activities. bit 5 = epsv error passive state - read only set by hardware to indicate that the node is error passive. reset by hardware to indicate that the node is either error active (boff = 0) or bus-off. bit 4 = srte simultaneous receive/transmit en- able - read/set/clear set by software to enable simultaneous transmis- sion and reception of a message passing the ac- ceptance filtering. allows to check the integrity of the communication path. reset by software to discard all messages trans- mitted by the node. allows remote and data frames to share the same identifier. bit 3 = nrtx no retransmission - read/set/clear set by software to disable the retransmission of un- successful messages. cleared by software to enable retransmission of messages until success is met. bit 2 = fsyn fast synchronization - read/set/clear set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for only 11 re- cessive bits in a row. cleared by software to enable the standard resyn- chronization when leaving standby mode, i.e. wait for 128 sequences of 11 recessive bits. bit 1 = wkps wake-up pulse - read/set/clear set by software to generate a dominant pulse when leaving standby mode. cleared by software for no dominant wake-up pulse. bit 0 = run can enable - read/set/clear set by software to leave stand-by mode after 128 sequences of 11 recessive bits or just 11 recessive bits if fsyn is set. cleared by software to request a switch to the stand-by or low-power mode as soon as any on-go- ing transfer is complete. read-back as 1 in the meantime to enable proper signalling of the stand- by state. the cpu clock may therefore be safely switched off whenever run is read as 0. 70 0 boff epsv srte nrtx fsyn wkps run 69/103 L9805 controller area network (contd) baud rate prescaler register (brpr) address: 005dh - read/write in stand-by mode reset value: 00h rjw[1:0] determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization. t rjw = t can * (rjw + 1) brp[5:0] determine the can system clock cycle time or time quanta which is used to build up the in- dividual bit timing. t can = t cpu * (brp + 1) where t cpu = time period of the cpu clock. the resulting baud rate can be computed by the for- mula: note: writing to this register is allowed only in stand-by mode to prevent any accidental can protocol violation through programming errors. bit timing register (btr) address: 005eh - read/write in stand-by mode reset value: 23h bs2[2:0] determine the length of bit segment 2. t bs2 = t can * (bs2 + 1) bs1[3:0] determine the length of bit segment 1. t bs1 = t can * (bs1 + 1) note: writing to this register is allowed only in stand-by mode to prevent any accidental can protocol violation through programming errors. page selection register (psr) address: 005fh - read/write reset value: 00h page[2:0] determine which buffer or filter page is mapped at addresses 0060h to 006fh. 70 rjw1 rjw0 brp5 brp4 brp3 brp2 brp1 brp0 br 1 t cpu brp 1 + () bs 1 bs 23 ++ () --------------------------------------------------------------------------------------------- - = 70 0 bs22 bs21 bs20 bs13 bs12 bs11 bs10 70 0 0 0 0 0 page2 page1 page0 pa g e 2 pa g e 1 pag e 0 pa g e t i t l e 000diagnosis 001buffer 1 010buffer 2 011buffer 3 100filters 101reserved 110reserved 111reserved 70/103 L9805 controller area network (contd) 5.6.4.2 paged registers last identifier high register (lidhr) read/write reset value: undefined lid[10:3] are the most significant 8 bits of the last identifier read on the can bus. last identifier low register (lidlr) read/write reset value: undefined lid[2:0] are the least significant 3 bits of the last identifier read on the can bus. lrtr is the last remote transmission request bit read on the can bus. ldlc[3:0] is the last data length code read on the can bus. transmit error counter reg. (tecr) read only reset value: 00h tec[7:0] is the least significant byte of the 9-bit transmit error counter implementing part of the fault confinement mechanism of the can protocol. in case of an error during transmission, this counter is incremented by 8. it is decremented by 1 after every successful transmission. when the counter value exceeds 127, the can controller enters the error passive state. when a value of 256 is reached, the can controller is disconnected from the bus. receive error counter reg. (recr) page: 00h read only reset value: 00h rec[7:0] is the receive error counter implement- ing part of the fault confinement mechanism of the can protocol. in case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the can stand- ard. after every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. when the counter value exceeds 127, the can controller enters the error passive state. identifier high registers (idhrx) read/write reset value: undefined id[10:3] are the most significant 8 bits of the 11-bit message identifier.the identifier acts as the mes- sages name, used for bus access arbitration and acceptance filtering. 70 lid10 lid9 lid8 lid7 lid6 lid5 lid4 lid3 70 lid2 lid1 lid0 lrtr ldlc3 ldlc2 ldlc1 ldlc0 70 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 70 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 70 id10id9id8id7id6id5id4id3 71/103 L9805 controller area network (contd) identifier low registers (idlrx) read/write reset value: undefined id[2:0] are the least significant 3 bits of the 11-bit message identifier. rtr is the remote transmission request bit. it is set to indicate a remote frame and reset to indicate a data frame. dlc[3:0] is the data length code. it gives the number of bytes in the data field of the mes- sage.the valid range is 0 to 8. data registers (data0-7x) read/write reset value: undefined data[7:0] is a message data byte. up to eight such bytes may be part of a message. writing to byte data7 initiates a transmit request and should al- ways be done even when data7 is not part of the message. buffer control/status regs. (bcsrx) read/write reset value: 00h bit 3 = acc acceptance code - read only set by hardware with the id of the highest priority filter which accepted the message stored in the buffer. acc = 0: match for filter/mask0. possible match for filter/mask1. acc = 1: no match for filter/mask0 and match for filter/mask1. reset by hardware when either rdy or rxif gets reset. bit 2 = rdy message ready - read/clear set by hardware to signal that a new error-free message is available (lock = 0) or that a trans- mission request is pending (lock = 1). cleared by software when lock = 0 to release the buffer and to clear the corresponding rxif bit in the interrupt status register. cleared by hardware when lock = 1 to indicate that the transmission request has been serviced or cancelled. bit 1 = busy busy buffer - read only set by hardware when the buffer is being filled (lock = 0) or emptied (lock = 1). reset by hardware when the buffer is not ac- cessed by the can core for transmission nor re- ception purposes. bit 0 = lock lock buffer - read/set/clear set by software to lock a buffer. no more message can be received into the buffer thus preserving its content and making it available for transmission. cleared by software to make the buffer available for reception. cancels any pending transmission request. cleared by hardware once a message has been successfully transmitted provided the early trans- mit interrupt mode is on. left untouched otherwise. note that in order to prevent any message corrup- tion or loss of context, lock cannot be set nor re- set while busy is set. trying to do so will result in lock not changing state. 70 id2 id1 id0 rtr dlc3 dlc2 dlc1 dlc0 70 data7 data6 data5 data4 data3 data2 data1 data0 70 0 0 0 0 acc rdy busy lock 72/103 L9805 controller area network (contd) filter high registers (fhrx) read/write reset value: undefined fil[11:3] are the most significant 8 bits of a 12-bit message filter. the acceptance filter is compared bit by bit with the identifier and the rtr bit of the incoming message. if there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer. filter low registers (flrx) read/write reset value: undefined fil[3:0] are the least significant 4 bits of a 12-bit message filter. mask high registers (mhrx) read/write reset value: undefined msk[11:3] are the most significant 8 bits of a 12- bit message mask. the acceptance mask defines which bits of the acceptance filter should match the identifier and the rtr bit of the incoming mes- sage. msk i = 0: dont care. msk i = 1: match required. mask low registers (mlrx) read/write reset value: undefined msk[3:0] are the least significant 4 bits of a 12-bit message mask. 70 fil11 fil10 fil9 fil8 fil7 fil6 fil5 fll4 70 fil3fil2fil1fil00000 70 msk11 msk10 msk9 msk8 msk7 msk6 msk5 msk4 70 msk3 msk2 msk1 msk0 0 0 0 0 73/103 L9805 controller area network (contd) figure 38. can register map interrupt status interrupt control control/status baud rate prescaler page selection paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg0 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 6fh 5ch 5ah 5bh 5dh 5fh 60h bit timing 5eh 74/103 L9805 controller area network (contd) figure 39. page maps 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh fhr0 flr0 mhr0 mlr0 fhr1 flr1 mhr1 mlr1 reserved idhr1 idlr1 data01 data11 data21 data31 data41 data51 data61 data71 reserved bcsr1 lidhr lidlr reserved tecr recr idhr2 idlr2 data02 data12 data22 data32 data42 data52 data62 data72 reserved bcsr2 idhr3 idlr3 data03 data13 data23 data33 data43 data53 data63 data73 reserved bcsr3 page 0 page 1 page 2 page 3 page 4 diagnosis buffer 1 buffer 2 buffer 3 acceptance filters 75/103 L9805 controller area network (contd) table 11. can register map and reset values address (hex.) pageregister name76543210 5ah isr rxif3 rxif2 rxif1 txif scif orif teif epnd reset value 0 0 0 0 0 0 0 0 5bh icr 0 esci rxie txie scie orie teie etx reset value 0 0 0 0 0 0 0 0 5ch csr 0 boff epsv srte nrtx fsyn wkps run reset value 0 0 0 0 0 0 0 0 5dh brpr rjw1 rjw0 brp5 brp4 brp3 brp2 brp1 brp0 reset value 0 0 0 0 0 0 0 0 5eh btr 0 bs22 bs21 bs20 bs13 bs12 bs11 bs10 reset value 0 0 1 0 0 0 1 1 5fh psr 0 0 0 0 0 page2 page1 page0 reset value 0 0 0 0 0 0 0 0 60h 00h lidhr lid10 lid9 lid8 lid7 lid6 lid5 lid4 lid3 reset value x x x x x x x x 01h- 03h idhrx id10 id9 id8 id7 id6 id5 id4 id3 reset value x x x x x x x x 60h/64h 04h fhrx fil11 fil10 fil9 fil8 fil7 fil6 fil5 fil4 reset value x x x x x x x x 61h 00h lidlr lid2 lid1 lid0 lrtr ldlc3 ldlc2 ldlc1 ldlc0 reset value x x x x x x x x 01h- 03h idlrx id2 id1 id0 rtr dlc3 dlc2 dlc1 dlc0 reset value x x x x x x x x 61h/65h 04h flrx fil3 fil2 fil1 fil0 0 0 0 0 reset value x x x x 0 0 0 0 62h-69h 01h- 03h data0-7x data7 data6 data5 data4 data3 data2 data1 data0 reset value x x x x x x x x 62h/66h 04h mhrx msk11 msk10 msk9 msk8 msk7 msk6 msk5 msk4 reset value x x x x x x x x 63h/ 67h 04h mlrx msk3 msk2 msk1 msk0 0 0 0 0 reset value x x x x 0 0 0 0 6eh 00h tecr tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 reset value 0 0 0 0 0 0 0 0 6fh 00h recr rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 reset value 0 0 0 0 0 0 0 0 01h- 03h bcsrx 0 0 0 0 acc rdy busy lock reset value 0 0 0 0 0 0 0 0 76/103 L9805 5.7 can bus transceiver 5.7.1 introduction the can bus transceiver allows the connection of the microcontroller, with can controller unit, to a can bus. the transmitter section drives the can bus while the receiver section senses the data on the bus. the can transceiver meets iso/dis 11898 up to 1 mbaud. 5.7.2 main features transmitter: C generation of differential output signals C short circuit protection from transients in auto- motive environment C slope control to reduce rfi and emi C high speed (up to 1mbaud) C if un-powered, L9805 can node does not disturb the bus lines (the transceiver is in recessive state). receiver: C differential input with high interference suppres- sion C common mode input voltage range (v com ) from -5 to 12v 5.7.3 functional description the can bus transceiver is used as an interface between a can controller and the physical bus. the device provides transmitting capability to the can controller. the transceiver has one logic in- put pin (tx), one logic output pin (rx) and two in- put/output pins for the electrical connections to the two bus wires (can_l and can_h). the mi- crocontroller sends data to the tx pin and it re- ceives data from the rx pin. the transmission slew-rates of can_h and can_l voltage are con- trolled to reduce rfi and emi. the transceiver is protected against short circuit or overcurrent: if i canh and/or i canl exceeds a current thresholds i sc , then the can_h and can_l power transis- tors are switched off and the transmission is disa- bled for t d =25 m s typical. 5.7.4 can transceiver disabling function the transceiver can be disabled and forced to move in a low power consumption mode, setting cands bit in dcsr register (see section 3.2.1 ). when the transceiver is in this mode it can not re- ceive nor transmit any information to the bus. the only way to have again on board the can capabil- ities is reset cands bit. the can protocol handler can not disable nor enable the transceiver and there is no way to communicate to the controller the transceiver is down. the disabling function has the only purpose to allow the reduction of the cur- rent consumption of the device in application not using the can at all or using it for particular func- tions (such like debugging). current consumption reduction, when disabling the trasceiver, can be as high as 15ma. note when the can capabilities of L9805 are not needed additional consumption reduction can be achieved putting the can controller in stand-by mode (see section 5.6.3.3 ). figure 40. can bus transceiver block diagram ?? + - tx0 rx0 can_h can_l overcurrent detection overcurrent detection power control r 2r r rr 2r vdd gnd 77/103 L9805 5.8 power bridge 5.8.1 introduction the power part of the device consists of two iden- tical independent dmos half bridges. it is suited to drive resistive and inductive loads. 5.8.2 main features the rdson of each of the 4 dmos transistors is 60 m w at 25c. the nominal current is 2a. the maximum current is 5a. the low-side switch is a n-channel dmos transis- tor while the high-side switch is a p-channel dmos transistor. therefore no charge pump is needed. an anti-crossconduction circuit is included: the low side dmos is switched on only when the high side is switched off and vice versa. this function avoid the two dmos are switched on together firing the high current path from battery to ground. the func- tion is obtained by sensing the gate voltage and therefore the delay between command and effec- tive switch on of the dmos doesnt have a fixed length. the mcu controls all operations of the power stage through the bcsr dedicated register. short circuit and overtemperature conditions are report- ed to the cpu using dedicated error flags. overtemperature and short circuit conditions switch off the bridge immediately without cpu in- tervention. the function of the flags is independent of the operation mode of the bridge (sink, source, z). in addition both the pwm modules can be directly connected to the power bridge. the power bridge offers then many driving mode alternatives: direct mode : the two half bridges are directly driv- en by in1 and in2 control bit in bcsr. pwm1 up/down brake mode : the output of pwm1 drives one side of the bridge while the other side is maintained in a fixed status. pwm1 symmetrical driving mode : pwm1 line drives directly and symmetrically both side of the bridge. pwm1/pwm2 mode : pwm1 drives one side while pwm2 drives the other (two independent half bridges). 5.8.3 functional description a schematic description of the power bridge cir- cuit is depicted in figure 41 . in this schematic the transistors must be considered in on condition when they gate is high (set). figure 41. power bridge schematic en bit in bcsr is the main enable signal, active high. if en = 0, all the bridge transistors are switched off (ul, ur, dl and dr are reset) and the outputs outl and outr are in high imped- ance state. being '0' the status after reset of en, the bridge is in safe condition (outl=outr=z). therefore the vbr pgnd outr vbl pgnd outl ul ur dl dr sc_ul ovt sc_dl ovt sc_dr ovt sc_ur ovt 78/103 L9805 safe condition is guaranteed in undervoltage con- dition (lvd reset) and in case of main clock (safe- guard reset) or software (watchdog reset) failures. each power dmos has its own over current detec- tor circuit generating sc_xx signals (see figure 41 ). sc_xx signals are ored together to generate sc flag in bcsr register. sc flag is then set by hardware as soon as one of the two outputs (or both) are short to battery, ground or if the two outputs are short together (load short). this read only bit is reset only by clearing the en bit. the rising edge of sc causes an interrupt request if the pie bit is set in bcsr register. when the current monitored in any of the four dmos of the bridge exceeds limit threshold (i sc ), the sc bit is set and the corresponding dmos is switched off after t scpi time. this function is domi- nant over any write from data bus by software (i. e. as long as sc is set, the bridge cannot be switched on). to switch the bridge on again the en bit must be cleared by software. this resets the sc bit. setting again en, the bridge is switched on. if the overcur- rent condition is still present, sc is set again (and a interrupt is generated when enabled). an internal thermal protection circuit monitors con- tinuously the temperature of the device and drives the ovt bit in bcsr register and, in turn, the ovt signal in figure 41 . the ovt flag is set as soon as the temperature of the chip exceeds thw and all the transistor of the bridge are switched off. this rising edge causes an interrupt request if the pie bit is set. this read only bit is reset only by clearing the en bit. this func- tion is dominant over any write from data bus by software (i. e. as long as ovt is set the bridge cannot be switched on). to switch the bridge on again the en bit must be cleared by software. this resets the ovt bit. set- ting again en, the bridge is switched on. if the overtemperature condition is still present, ovt is set again (and a interrupt is generated when ena- bled). 5.8.4 interrupt generation interrupt generation is controlled by pdie bit in bcsr register. when this bit is set overtempera- ture and short-circuit conditions generate an inter- rupt as described in section 5.8.3 . setting pdie when sc and/or ovt flag are set, immediately generates an interrupt request. the interrupt request of the power bridge is cleared when the en bit is cleared by software. 5.8.5 operating modes the status of the outl and outr power outputs is controlled by in1, in2, en, pwm_en and dir bit in bcsr register, plus the pwm1 and pwm2 line, according to the functional description table ( table 12 ). note the functional description table ( table 12 ) uses symbols ul,r (up left or right) and dr,l (down left or right) to indicate the driving signal of the four dmos. conventionally a transistor is in the on status when its driving signal is set (1) while it is in off status when the driving signal is re- set (0). 79/103 L9805 table 12. functional description table drive en pwm_en dir pwm1 in1 in2 ul dl ur dr operation configuration 0 x xxxx0000 in hibit direct mode 1 0 xx000101 brake full or two half bridges 1 0 xx010110 back full or two half bridges 1 0 xx101001 forward full or two half bridges 1 0 xx111010 brake full or two half bridges pwm1 up brake mode 1 1 0 0001010 brakefull bridge 1 1 0 1001001 forwardfull bridge 1 1 1 0001010 brakefull bridge 1 1 1 1000110 backfull bridge 80/103 L9805 note the dir signal is internally synchronized with the pwm1 and pwm2 signals according to the selected driving mode. after writing the dir bit in bcsr register, the direction changes in corre- spondence with the first rising edge of pwm1. the same procedure is used in the case of pwm2. this allows the proper control of the direction changes. when the pwm signal is 0% or 100%, being no edges available, the dir bit cant be latched and the direction does not change until a pwm edge occurs. pwm1 down brake mode 1 1 0 0010101 brakefull bridge 1 1 0 1011001 forwardfull bridge 1 1 1 0010101 brakefull bridge 1 1 1 1010110 backfull bridge pwm1 symmetrical driving mode 1 1 0 0100110 backfull bridge 1 1 0 1101001 forwardfull bridge 1 1 1 0101001 forwardfull bridge 1 1 1 1100110 backfull bridge pwm1/pwm2 mode 1 1 0 1 1 pwm1 pwm1 pwm2 pwm2 pwm1 ->left pwm2->right two half bridges 1 1 1 1 1 pwm1 pwm1 pwm2 pwm2 pwm1 ->left pwm2 ->right two half bridges drive en pwm_en dir pwm1 in1 in2 ul dl ur dr operation configuration 81/103 L9805 figure 42. example - power bridge waveform, pwm up brake driving mode 5.8.6 register description the power section is controlled by the microcon- troller through the following register: power bridge control status regis- ter (pbcsr) address: 0021h - read/write reset value: 00000000 bit 0 = en: power bridge enable. when reset the bridge is disabled and outl and outr are in high impedance condition. bit 1 = pwm_en : pwm driving enable. when reset the bridge is driven directly by in1 and in2 bit (di- rect mode). when set the driving is made by pwm1 and/or pwm2 bit according to the opera- tion mode selected by in1 and in2 bit. bit 2 = in1 : left half bridge control bit if pwm_en=0, driving mode selection bit if pwm_en=1. bit 3 = in2 : right half bridge control bit if pwm_en=0, driving mode selection bit if pwm_en=1. the following table summarizes the driving mode selection made by pwm_en, in1 and in2 bit bit 4 = dir : direction bit. this bit is meaningless when pwm_en=0. when pwm_en is set the dir bit controls the driving direction of the bridge. in order to implement a precise control of the direc- tion changes, dir value is latched by the rising edge of the pwm signal driving the bridge. when the signal does not have edges (i.e. pwm = 0% or 100%) the dir bit can not be latched and the driv- ing direction does not change even changing dir bit in bcsr. bit 5 = sc : short circuit flag (read only) bit 6 = ovt : overtemperature flag (read only) bit 7 = pie : power section interrupt enable. pwm1 dir ul dl ur dr outl outr back back back brake brake brake fwd fwd brake brake 70 pie ovt sc dir in2 in1 pwm_ en en pwm_en in1 in2 driving mode 0 x x direct 1 0 0 pwm1 up braking 1 0 1 pwm1 down braking 1 1 0 pwm1 symmetrical 1 1 1 pwm1/pwm2 82/103 L9805 5.9 eeprom (eep) 5.9.1 introduction the electrically erasable programmable read only memory is used to store data that need a non volatile back-up. the use of the eeprom requires a basic protocol described in this chapter. software or hardware reset and halt modes are managed immediately, stopping the action in progress. wait mode does not affect the program- ming of the eeprom. the read operation of this memory is the same of a read-only-memory or ram. the erase and pro- gramming cycles are controlled by an eeprom control register. the user can program 1 to 4 bytes at the same programming cycle providing that the high part of the address is the same for the bytes to be written (only address bits a1 and a0 can change). the eeprom is mono-voltage. a charge pump generates the high voltage internally to enable the erase and programming cycles. the erase and programming cycles are chained automatically. the global programming cycle duration is control- led by an internal circuit. figure 43. eeprom block diagram buffer row decoder 4*8 bits data latches data multiplexer high voltage pump eeprom memory matrix 1 row = 4 * 8 bits address decoder address bus data bus e2ite e2lat e2pgm eepcr . . . . . . 32 32 8 8 4 4 12 interrupt request falling edge detector 8 bit read amplifiers 83/103 L9805 5.9.2 functional description 5.9.2.1 read operation (e2lat=0) the eeprom can be read as a normal rom/ram location when the e2lat bit of the cr register is cleared. the address decoder selects the desired byte. the 8 sense amplifiers evaluate the stored byte which is put on the data bus. 5.9.2.2 write operation (e2lat=1) the eeprom programming flowchart is shown in figure 45 . to access the write mode, e2lat bit must be set. then when a write access to the eeprom occurs, the value on the data bus is latched on the 8 data latches depending on the address. to program the memory, the e2pgm bit must be set, so the pro- gramming cycle starts. at the end of the cycle, the e2pgm bit and e2lat bit are cleared, and an in- terrupt could be generated id e2ite is set. 5.9.2.3 wait mode the eeprom can enter the wait mode by execut- ing the wait instruction of the micro-controller. the eeprom will effectively enter this mode if there is no programming in progress, in such a case the eeprom will finish the cycle and then enter this low consumption mode. 5.9.2.4 halt mode the eeprom enters the halt mode if the micro- controller did execute the halt instruction. the eeprom will stop the function in progress, and will enter in this low consumption mode. figure 44. eeprom programming cycle erase cycle write cycle tprog read operation allowed read operation not possible internal programming voltage write of data latches e2lat e2pgm interrupt request interrupt vector fetch 84/103 L9805 figure 45. eeprom programming flowchart 5.9.3 register description eeprom control register (eecr) address: 002ch - read/write reset value: 0000 0000 (00h) bit 7:3 = reserved, forced by hardware to 0. bit 2 = e2ite : interrupt enable. this bit is set and cleared by software. 0: interrupt disabled 1: interrupt enabled when the programming cycle is finished (e2pgm toggle from 1 to 0), an interrupt is generated only if e2ite is high. the interrupt is automatically cleared when the micro-controller enters the eep- rom interrupt routine. bit 1 = e2lat : read/write mode. this bit is set by software. it is cleared by hard- ware at the end of the programming cycle. it can be cleared by software only if e2pgm=0. 0: read mode 1: write mode when e2lat=1, if the e2pgm bit is low and the micro-controller is in write mode, the 8 bit data bus is stored in one of the four groups of 8 bit data latches, selected by the address. this happens every time the device executes an eeprom write instruction. if e2pgm remains low, the content of the 8 bit data latches is not transferred into the ma- trix, because the high voltage charge-pump does not start. the 8 data latches are selected by the lower part of the address (a<1:0> bits). if 4 con- secutive write instructions are executed, by sweeping from a<1:0>=0h to a<1:0>=3h, with the e2lat=1 e2pgm=0 (write mode) write bytes in eeprom e2lat=1 e2pgm=1 (start programming cycle) wait for end of programming (e2lat=0 or interrupt) write 1 to 4 bytes in the same row (with the same 12 most significant bits of the address) e2lat=0 e2pgm=0 (read mode) 70 00000e2itee2late2pgm 85/103 L9805 same higher part of the address, all the 4 groups of data latches will be written, and they will be ready to write a whole row of the eeprom matrix, as soon as e2pgm goes high and the charge-pump starts. if only one write instruction is executed be- fore e2pgm goes high, only one group of data latches will be selected and only one byte of the matrix will be written. at the end of the program- ming cycle, e2lat bit is automatically cleared, and the data latches are cleared. bit 0 = e2pgm : programming control. this bit is set by software to begin the program- ming cycle. at the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the e2ite bit is set. 0: programming finished or not started 1: programming cycle is in progress note : if the e2pgm bit is cleared during the pro- gramming cycle, the memory data is not guaran- teed. note : care should be taken during the program- ming cycle. writing to the same memory location will over-program the memory (logical and be- tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of e2lat bit. it is not possible to read the latched data. special management of wrong eeprom access: if a read happens while e2lat=1, then the data bus will not be driven. if a write access happens while e2lat=0, then the data on the bus will not be latched. the data latches are cleared when the user sets e2lat bit. 86/103 L9805 6 instruction set 6.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000 - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimize the use of long and short addressing modes. table 13. st7 addressing mode overview: addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 87/103 L9805 instruction set overview (contd) inherent: all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. immediate: immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value.. direct (short, long): in direct instructions, the operands are referenced by their memory address, which follows the op- code. the direct addressing mode consists of two sub- modes: direct (short): the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long): the address is a word, thus allowing 64kb ad- dressing space, but requires 2 bytes after the op- code. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest pow- er mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations available long and short direct instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- structions operations bcp bit compare short direct instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine 88/103 L9805 instruction set overview (contd) indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset which follows the opcode. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long): the offset is a word, thus allowing 64kb address- ing space and requires 2 bytes after the opcode. indirect (short, long): the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short): the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long): the pointer address is a byte, the pointer size is a word, thus allowing 64kb addressing space, and no offset, long and short indexed instruction function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- structions operations bcp bit compare no offset and short indexed instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2s complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available long and short indirect instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- structions operations bcp bit compare short indirect instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2s complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine 89/103 L9805 instruction set overview (contd) indirect indexed (short, long): this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short): the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long): the pointer address is a byte, the pointer size is a word, thus allowing 64kb addressing space, and requires 1 byte after the opcode. relative mode (direct, indirect): this addressing mode is used to modify the pc register value, by adding an 8 bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct): the offset is following the opcode. relative (indirect): the offset is defined in memory, which address follows the opcode. long and short indirect indexed instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- structions operations bcp bit compare short indirect indexed instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative 90/103 L9805 instruction set overview (contd) 6.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent probate pockets are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf 91/103 L9805 instruction set overview (contd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port a int pin = 1 (no port a interrupts) jril jump if port a int pin = 0 (port a interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > 92/103 L9805 instruction set overview (contd) jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m hinzc pop cc cc m push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z 93/103 L9805 7 electrical characteristics 7.1 absolute maximum ratings this device contains circuitry to protect the inputs against damage due to high static voltage or elec- tric fields. nevertheless, it is recommended that normal precautions be observed in order to avoid subjecting this high-impedance circuit to voltage above those quoted in the absolute maximum rat- ings. for proper operation, it is recommended that the input voltage v in , on the digital pins, be con- strained within the range: (gnd - 0.3v) v in (v dd + 0.3v) to enhance reliability of operation, it is recom- mended to configure unused i/os as inputs and to connect them to an appropriate logic voltage level such as gnd or v dd . all the voltage in the following tables are refer- enced to gnd. table 14. absolute maximum ratings (voltage referenced to gnd) symbol ratings value unit vbr vbl = vb vb1 supply voltage t = 10m iso transients t = 400ms 1) note 1. iso transient must not reset the device 0 to 18 0 to 24 0 to 40 v |agnd - gnd| max. variations (ground line) 50 mv t stg storage temperature range -65 to +150 c t j junction temperature 150 c esd esd susceptibility 2000 v v lv input voltage, low voltage pins gnd - 0.3 to v dd + 0.3 v v pwm pin voltage, pwmi, pwmo pins gnd - 18 to vb v v can pin voltage, can_h, can_l pins gnd - 18 to vb v i in input current (low voltage pins) -25.....+25 ma 94/103 L9805 7.2 power considerations the average chip-junction temperature, t j , in de- grees celsius, may be calculated using the follow- ing equation: t j = t a + (p d x q ja ) (1)* where: C t a is the ambient temperature in c, C q ja is the package junction-to-ambient thermal resistance, in c/w, C p d is the sum of p int and p i/o , C p int is the product of i 1 and vb, plus the power dissipated by the power bridge, expressed in watts. this is the chip internal power C p i/o represents the power dissipation on input and output pins; user determined. for most applications p i/o < 95/103 L9805 figure 46. hiquad-64: q ja figure 47. hiquad-64: thermal impedance 1 2 3 4 5 6 7 dissipated power (w) 12 14 16 18 20 22 24 rth j-c (oc/w) die size 6x6 mm2 t amb. 22 oc natural convection 2s1p 1oz pcb multilayer optimised pcb 0 0 1 10 100 1,000 0 5 10 15 20 zth (oc/w) time (s) die size 6x6 mm2 power 6 w t amb. 22 oc natural convection 2s1p 1oz pcb multilayer optimised pcb
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